Failure detection circuit, semiconductor device and failure detection method

Patent metadata

Field	Value
Publication number	US-2025102571-A1
Application number	US-202418773937-A
Country	US
Kind code	A1
Filing date	Jul 16, 2024
Priority date	Sep 22, 2023
Publication date	Mar 27, 2025
Grant date	—

Abstract

A failure detection circuit is provided in the target circuit having a first circuit area for operating in synchronization with the first clock signal, a first detection circuit for outputting a first detection result obtained by transitioning the voltage level in synchronization with the first clock signal, the first clock signal a second detection circuit for outputting a second detection result obtained by transitioning the voltage level in synchronization with, and a first comparison circuit for outputting a first comparison result by comparing the first detection result and the second detection result. Accordingly, by the failure detection circuit, it is possible to detect the failure accurately.

First claim

What is claimed is:

1 . A fault detection circuit provided in a target circuit having a first circuit area that operates in synchronization with a first clock signal comprising:
a first detection circuit for outputting a first detection result obtained by transitioning a voltage level in synchronization with the first clock signal, a second detection circuit for outputting a second detection result obtained level by transitioning the voltage in synchronization with the first clock signal, and a first comparison circuit for outputting a first comparison result by comparing the first detection result and the second detection result.

2 . The failure detection circuit according to claim 1 ,
when the first detection result and the second detection result match, the first comparison circuit outputs the first comparison result indicating that a failure has not occurred in the first circuit area, when the first detection result and the second detection result do not match, the first comparison circuit outputs the first comparison result indicating that a failure has occurred in the first circuit area.

3 . The failure detection circuit according to claim 1 ,
wherein the first detection circuit outputs a third detection result obtained by transitioning a voltage level to the first detection result in synchronization with the first clock signal, wherein the second detection circuit outputs a fourth detection result obtained by transitioning the voltage level to the second detection result in synchronization with the first clock signal, wherein the first comparison circuit compares the first detection result with the second detection result, further compares the third detection result with the fourth detection result, and outputs the first comparison result.

4 . The failure detection circuit according to claim 3 ,
when the first detection result and the second detection result match, and when the third detection result and the fourth detection result match, the first comparison circuit outputs a first comparison result indicating that a failure has not occurred in the first circuit area, when the first detection result and the second detection result do not match, or when the third detection result and the fourth detection result do not match, the first comparison circuit outputs a first comparison result indicating that a failure has occurred in the first circuit area.

5 . The failure detection circuit according to claim 1 ,
the first detection circuit further comprising:
a first selector for selecting and outputting either a first initial value that is one of 0 and 1 or the first detection result based on a first reset signal;
a first flip-flop for capturing and outputting an output signal of the first selector in synchronization with the first clock signal; and
a first inverter for inverting the output signal of the first flip-flop and outputting the first detection result, the second detection circuit further comprising:
a second selector for selecting and outputting by selecting either the first initial value or the first detection result based on the first reset signal;
a second flip-flop for capturing and outputting captures an output signal of the second selector in synchronization with the first clock signal; and
a second inverter for inverting the output signal of the second flip-flop and outputting the second detection result.

6 . The failure detection circuit according to claim 3 ,
the first detection circuit further comprising:
a first selector for selecting and outputting either a first initial value that is one of 0 and 1 or the first detection result based on a first reset signal;
a first flip-flop for capturing and outputting an output signal of the first selector in synchronization with the first clock signal; and
a first inverter for inverting the output signal of the first flip-flop and outputting the first detection result, the second detection circuit further comprising:
a second selector for selecting and outputting by selecting either the first initial value of the first detection result based on the first reset signal;
a second flip-flop for capturing and outputting an output signal of the second selector in synchronization with the first clock signal; and
a second inverter for inverting the output signal of the second flip-flop and outputting the second detection result,
the first detection circuit further comprising: a third selector for selecting and outputting either a second initial value that is other of 0 and 1 or the third detection result based on the first reset signal; a third flip-flop for capturing and outputting an output signal of the third selector in synchronization with the first clock signal; and a third inverter for inverting the output signal of the third flip-flop and outputting the third detection result, the second detection circuit further comprising: a fourth selector for selecting and outputting by selecting either the second initial value or the fourth detection result based on the first reset signal; a fourth flip-flop for capturing and outputting an output signal of the fourth selector in synchronization with the first clock signal; and a fourth inverter for inverting the output signal of the fourth flip-flop and outputting the second detection result.

7 . The failure detection circuit according to claim 1 ,
the target circuit further includes a second circuit area which operates in synchronization with the second clock signal, a third detection circuit for outputting a third detection result of transitioning the voltage level in synchronization with the second clock signal, a fourth detection circuit for outputting a fourth detection result obtained by transitioning the voltage level in synchronization with the second clock signal, a second comparison circuit for outputting a second comparison result by comparing the third detection result and the fourth detection result.

8 . The failure detection circuit according to claim 7 ,
when the first detection result and the second detection result match, the first comparison circuit outputs a first comparison result indicating that a failure has not occurred in the first circuit area of the target circuit, when the first detection result and the second detection result do not match, the first comparison circuit outputs a first comparison result indicating that a failure has occurred in the first circuit area of the target circuit, when the third detection result and the fourth detection result match, the second comparison circuit outputs a second comparison result indicating that a failure has not occurred in the second circuit area of the target circuit, when the third detection result and the fourth detection result do not match, the second comparison circuit outputs a second comparison result indicating that a failure has occurred in the second circuit area of the target circuit.

9 . The failure detection circuit according to claim 7 ,
the first circuit area and the second circuit area are driven by different power supply voltages, the first detection circuit, the second detection circuit, and the first comparison circuit are disposed in the first circuit area, the third detection circuit, the fourth detection circuit, and the second comparison circuit are disposed in the second circuit area.

10 . A semiconductor device is configured the failure detection circuit and the target circuit according to claim 1 .

11 . A failure detection method by the failure detection circuit provided in the target circuit having a first circuit area that operates in synchronization with a first clock signal,
by using a first detection circuit,

Assignees

• Renesas Electronics Corp

Inventors

• Miyaguchi Akira
• Kawakita Daisuke
• Hirano Masaaki
• Suzuki Shogo

Classifications

• G01R19/16576

  comparing DC or AC voltage with one threshold (G01R19/16514, G01R19/16519, G01R19/16528, G01R19/16533 and G01R19/1659 take precedence) · CPC title

• G01R31/3183

  Generation of test inputs, e.g. test vectors, patterns or sequences · CPC title

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/31727 Primary

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G01R31/31703 Primary

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title