Hybrid methods and structures for increasing capacitance density in integrated passive devices

Patent metadata

Field	Value
Publication number	US-2025098184-A1
Application number	US-202318470582-A
Country	US
Kind code	A1
Filing date	Sep 20, 2023
Priority date	Sep 20, 2023
Publication date	Mar 20, 2025
Grant date	—

Abstract

A method for increasing capacitance density within an integrated passive device can include forming a first trench capacitor within a substrate, forming a second trench capacitor within an insulating layer overlying the substrate, and connecting the first and second trench capacitors through connection vias that extend through the insulating layer to form an integrated passive device (IPD) capacitor. A high capacitance density device can include a stacked and co-integrated architecture of two or more tiers of trench capacitors.

First claim

What is claimed is:

1 . An integrated passive device capacitor comprising:
a first trench capacitor disposed within a substrate; and a second trench capacitor disposed over the substrate, wherein
a primary electrode of the first trench capacitor is electrically connected to a primary electrode of the second trench capacitor; and
a secondary electrode of the first trench capacitor is electrically connected to a secondary electrode of the second trench capacitor.

2 . The integrated passive device capacitor of claim 1 , wherein the substrate comprises glass or a semiconductor.

3 . The integrated passive device capacitor of claim 1 , wherein the first trench capacitor and the second trench capacitor are interconnected in a manner effective to increase a capacitance density of the integrated passive device capacitor relative to a capacitance density of the first trench capacitor and the second trench capacitor.

4 . The integrated passive device capacitor of claim 1 , wherein the second trench capacitor is disposed within a layer of insulating material overlying the substrate and respective primary electrodes, secondary electrodes, and dielectric layers of the first and second trench capacitors are connected through material filled vias that extend through the layer of insulating material.

5 . The integrated passive device capacitor of claim 1 , comprising a multilayer stack of N co-integrated trench capacitors, wherein N>2.

6 . A method comprising:
forming a first trench capacitor within a substrate; forming a second trench capacitor within an insulating layer overlying the substrate; and connecting the first and second trench capacitors through connection vias that extend through the insulating layer to form an integrated passive device (IPD) capacitor.

7 . The method of claim 6 , wherein a capacitance density of the integrated passive device (IPD) capacitor is approximately equal to a sum of a capacitance density of the first and second trench capacitors.

8 . The method of claim 6 , wherein the substrate comprises glass or a semiconductor.

9 . The method of claim 6 , wherein forming the first trench capacitor comprises successively forming a primary electrode layer, a dielectric layer, and a secondary electrode layer within a trench formed in the substrate.

10 . The method of claim 6 , comprising forming the insulating layer directly over portions of the first trench capacitor.

11 . The method of claim 6 , wherein forming the second trench capacitor comprises successively forming a primary electrode layer, a dielectric layer, and a secondary electrode layer within a trench formed in the insulating layer.

12 . The method of claim 6 , wherein the first and second trench capacitors are connected in parallel.

13 . The method of claim 6 , wherein connecting the first and second trench capacitors comprises:
electrically connecting a primary electrode layer within the first trench capacitor with a primary electrode layer within the second trench capacitor; connecting a dielectric layer within the first trench capacitor with a dielectric layer within the second trench capacitor, and electrically connecting a secondary electrode layer within the first trench capacitor with a secondary electrode layer within the second trench capacitor.

14 . The method of claim 6 , further comprising forming a redistribution structure over the second trench capacitor and forming an interconnect structure over the redistribution structure.

15 . The method of claim 6 , further comprising:
forming a third trench capacitor within a second insulating layer overlying the insulating layer; and connecting the second and third trench capacitors through connection vias that extend through the second insulating layer.

16 . A method comprising:
forming a first trench within a substrate; forming a first trench capacitor within the first trench, the first trench capacitor comprising a primary electrode, a dielectric layer overlying the primary electrode, and a secondary electrode overlying the dielectric layer; forming an insulating layer over the first trench capacitor and over the substrate; forming a second trench within the insulating layer; forming a second trench capacitor within the second trench, the second trench capacitor comprising a primary electrode, a dielectric layer overlying the primary electrode, and a secondary electrode overlying the dielectric layer; forming vias that extend entirely through the insulating layer; forming a conductive layer within primary vias to electrically connect the primary electrode of the first trench capacitor with the primary electrode of the second trench capacitor; forming a conductive layer within secondary vias to electrically connect the secondary electrode of the first trench capacitor with the secondary electrode of the second trench capacitor; and forming a dielectric layer within tertiary vias to connect the dielectric layer of the first trench capacitor with the dielectric layer of the second trench capacitor to form an integrated passive device capacitor.

17 . The method of claim 16 , wherein the insulating layer is formed directly over at least a portion of the first trench capacitor.

18 . The method of claim 16 , wherein the vias are formed using an anisotropic etch.

19 . The method of claim 16 , wherein:
the primary electrode of the first trench capacitor, the primary electrode of the second trench capacitor, and the conductive layer within the primary vias are compositionally equivalent; and the secondary electrode of the first trench capacitor, the secondary electrode of the second trench capacitor, and the conductive layer within the secondary vias are compositionally equivalent.

20 . The method of claim 16 , wherein a capacitance density of the integrated passive device capacitor is greater than a capacitance density of the first trench capacitor and greater than a capacitance density of the second trench capacitor.

Assignees

• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Alam Arsalan
• Srivastava Anadi
• Sidhu Rajen Singh
• Pfeiffenberger Alexander Helmut
• Wang Liwei

Classifications

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H10D1/716

  having vertical extensions · CPC title