Semiconductor memory device and method of manufacturing semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2025098164-A1
Application number	US-202418826326-A
Country	US
Kind code	A1
Filing date	Sep 6, 2024
Priority date	Sep 20, 2023
Publication date	Mar 20, 2025
Grant date	—

Abstract

According to one embodiment, a semiconductor memory device includes first and second stacked bodies. In each of the first and second stacked bodies, conductive layers and insulating layers are alternately stacked one by one. The semiconductor memory device includes first and second bridging members. The first bridging member penetrates the first stacked body and connects first interlayer insulating films covering a first staircase part on both sides. The first bridging member is provided on an upper end of a first platy member. The second bridging member penetrates the second stacked body and connects second interlayer insulating films covering a second staircase part on both sides. The second bridging member is provided on an upper end of a second platy member. Lower ends of the first and second bridging members are positioned above uppermost conductive layers of the first and second stacked bodies, respectively.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a first stacked body in which first conductive layers and first insulating layers are alternately stacked one by one, the first conductive layers including a first staircase part in a staircase shape extending in a first direction intersecting with a stacking direction of the first conductive layers; a first interlayer insulating film covering the first staircase part; a second stacked body in which second conductive layers and second insulating layers are alternately stacked one by one, the second stacked body being provided above the first stacked body, the second conductive layers including a second staircase part in a staircase shape continuous to the first staircase part in the first direction; a second interlayer insulating film covering the second staircase part; a first platy member extending in the first direction and penetrating the first stacked body in the stacking direction; a second platy member extending in the first direction and penetrating the second stacked body in the stacking direction, the second platy member being connected to an upper end of the first platy member; a first bridging member provided on the upper end of the first platy member, the first bridging member connecting the first interlayer insulating films on both sides of the first platy member; and a second bridging member provided on an upper end of the second platy member, the second bridging member connecting the second interlayer insulating films on both sides of the second platy member, wherein lower ends of the first and second bridging members are positioned above uppermost first and second conductive layers in the first and second stacked bodies, respectively.

2 . The semiconductor memory device according to claim 1 , wherein
the first and second platy members and at least part of the first bridging member each include a conductive member including a conductive material, and a width in a second direction of the conductive member in the first bridging member is less than or equal to a width in the second direction of the conductive member in the upper end of the first platy member, the second direction being a direction intersecting with the first direction and the stacking direction.

3 . The semiconductor memory device according to claim 2 , wherein side surfaces in the second direction of the first and second platy members have a wave shape with periodicity in the first direction.

4 . The semiconductor memory device according to claim 3 , wherein the first and second platy members each include pillar-like members extending in the stacking direction, the pillar-like members being linked to each other in the first direction.

5 . The semiconductor memory device according to claim 3 , wherein
the first bridging member includes at least one material among polysilicon and silicon carbonitride, and the second bridging member includes at least any material among silicon oxide, polysilicon, and silicon carbonitride.

6 . The semiconductor memory device according to claim 1 , wherein the first bridging member is constituted by multiple bridging members arranged in the first direction at intervals being partly different.

7 . The semiconductor memory device according to claim 1 , wherein at least part of the first bridging member does not overlap in the stacking direction with at least part of the second bridging member.

8 . The semiconductor memory device according to claim 4 , wherein
the first bridging member is provided to stride over the pillar-like members of the first and second platy members in the first direction, and the first bridging member includes pillar-like members connected to the first and second platy members in the stacking direction and not linked to each other.

9 . The semiconductor memory device according to claim 2 , wherein the width in the second direction of the conductive member in the first bridging member is wider than a width in the second direction of the conductive member in a lower end of the second platy member.

10 . A semiconductor memory device comprising:
a first stacked body in which first conductive layers and first insulating layers are alternately stacked one by one, the first conductive layers including a first staircase part in a staircase shape extending in a first direction intersecting with a stacking direction of the first conductive layers; a first interlayer insulating film covering the first staircase part; a second stacked body in which second conductive layers and second insulating layers are alternately stacked one by one, the second stacked body being provided above the first stacked body, the second conductive layers including a second staircase part in a staircase shape continuous to the first staircase part in the first direction; a second interlayer insulating film covering the second staircase part; a first platy member extending in the first direction and penetrating the first stacked body in the stacking direction, the first platy member including a first insulating material; a second platy member extending in the first direction and penetrating the second stacked body in the stacking direction, the second platy member being connected to an upper end of the first platy member, the second platy member including the first insulating material; and a bridging member provided on the upper end of the first platy member, the first bridging member connecting the first interlayer insulating films on both sides of the first platy member, the first bridging member including a material different from the first insulating material, wherein side surfaces in a second direction of the first and second platy members have a wave shape with periodicity in the first direction, the second direction being a direction intersecting with the first direction and the stacking direction, and a lower end of the bridging member is positioned above an uppermost first conductive layer in the first stacked body.

11 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a first stacked body in which first insulating layers and second insulating layers are alternately stacked one by one, the second insulating layers including a first staircase part processed in a staircase shape extending in a first direction intersecting with a stacking direction of the second insulating layers; forming a first interlayer insulating film to cover the first staircase part; forming a first groove, the first groove penetrating the first stacked body in the stacking direction and extending in the first direction; forming a first bridging member in an upper end of the first groove, the first bridging member connecting the first interlayer insulating films on both sides of the first groove, the first bridging member including a lower end positioned above the second insulating layer; forming a second stacked body in which third insulating layers and fourth insulating layers are alternately stacked one by one in the stacking direction, the second stacked body being formed above the first stacked body, the fourth insulating layers including a second staircase part processed in a staircase shape continuous to the first staircase part in the first direction; forming a second interlayer insulating film to cover the second staircase part; forming a second groove, the second groove penetrating the second stacked body in the stacking direction and extending in the first direction; and forming a second bridging member in an upper end of the second groove, the second bridging member connecting the second interlayer insulating films on both sides of the second groove, th

Assignees

• Kioxia Corp

Inventors

• Nishimura Toshimichi
• Takeuchi Yosuke

Classifications

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title