Stacked semiconductor device

Patent metadata

Field	Value
Publication number	US-2025096202-A1
Application number	US-202418788541-A
Country	US
Kind code	A1
Filing date	Jul 30, 2024
Priority date	Sep 19, 2023
Publication date	Mar 20, 2025
Grant date	—

Abstract

A semiconductor device assembly is provided. The semiconductor device assembly includes a logic die, a first plurality of stacked memory dies electrically coupled with the logic die, and a second plurality of stacked memory dies mounted on and electrically coupled with the first plurality of stacked memory dies. A first dielectric material is disposed around the first plurality of stacked memory dies. A second dielectric material is disposed at the first dielectric material and surrounding the second plurality of stacked memory dies. A third dielectric material is disposed between the first plurality of stacked memory dies and the second plurality of stacked memory dies and between the first dielectric material and the second dielectric material.

First claim

What is claimed is:

1 . A semiconductor device assembly, comprising:
a logic die; a first plurality of stacked memory dies electrically coupled with the logic die at a first lateral location; a second plurality of stacked memory dies electrically coupled with the logic die at a second lateral location different from the first lateral location; a first dielectric material disposed at the logic die between the first plurality of stacked memory dies and the second plurality of stacked memory dies; a third plurality of stacked memory dies mounted on and electrically coupled with the first plurality of stacked memory dies; a fourth plurality of stacked memory dies mounted on and electrically coupled with the second plurality of stacked memory dies; a second dielectric material disposed at the first dielectric material between the third plurality of stacked memory dies and the fourth plurality of stacked memory dies; and a third dielectric material disposed over the first plurality of stacked memory dies, the second plurality of stacked memory dies, and the first dielectric layer, the third dielectric material coupling the third plurality of stacked memory dies, the fourth plurality of stacked memory dies, and the second dielectric material couple with the first plurality of stacked memory dies, the second plurality of stacked memory dies, and the first dielectric layer, respectively.

2 . The semiconductor device assembly of claim 1 , wherein a first thickness of the third dielectric material between the first dielectric material and the second dielectric material is greater than a second thickness of the third dielectric material between the third plurality of stacked memory dies and the first plurality of stacked memory dies.

3 . The semiconductor device assembly of claim 1 , wherein the first plurality of stacked memory dies includes respective first interconnects coupling a respective first memory die and a respective second memory die of the first plurality of stacked memory dies, the respective first interconnects electrically coupled between respective first contact pads at the respective first memory die and respective second contact pads at the respective second memory die.

4 . The semiconductor device assembly of claim 3 , wherein:
the first plurality of stacked memory dies includes a top memory die having third contact pads; the third plurality of stacked memory dies includes a bottom memory die having fourth contact pads; the semiconductor device assembly includes second interconnects electrically coupling the third contact pads and the fourth contact pads; and the third contact pads and the fourth contact pads have a greater misalignment than the respective first contact pads and the respective second contact pads.

5 . The semiconductor device assembly of claim 1 , further comprising:
a fifth plurality of stacked memory dies mounted on and electrically coupled with the third plurality of stacked memory dies; a sixth plurality of stacked memory dies mounted on and electrically coupled with the fourth plurality of stacked memory dies; and a fourth dielectric material disposed at the second dielectric material between the fifth plurality of stacked memory dies and the sixth plurality of stacked memory dies.

6 . The semiconductor device assembly of claim 1 , wherein the first plurality of memory dies includes four memory dies.

7 . A method for fabricating a semiconductor device assembly, comprising:
providing a wafer of logic dies; providing a first plurality of stacked semiconductor dies; providing a second plurality of stacked semiconductor dies; coupling the first plurality of stacked semiconductor dies to the wafer of logic dies at a first lateral location; coupling the second plurality of stacked semiconductor dies to the wafer of logic dies at a second lateral location different from the first lateral location; disposing a first dielectric material at the wafer of logic dies between the first plurality of stacked semiconductor dies and the second plurality of stacked semiconductor dies; providing a third plurality of stacked semiconductor dies; providing a fourth plurality of stacked semiconductor dies; mounting the third plurality of stacked semiconductor dies to the first plurality of stacked semiconductor dies to electrically couple the third plurality of stacked semiconductor dies and the first plurality of stacked semiconductor dies; mounting the fourth plurality of stacked semiconductor dies to the first plurality of stacked semiconductor dies to electrically couple the fourth plurality of stacked semiconductor dies and the second plurality of stacked semiconductor dies; and disposing a second dielectric material at the first dielectric material between the third plurality of stacked semiconductor dies and the fourth plurality of stacked semiconductor dies.

8 . The method of claim 7 , further comprising disposing a third dielectric material between the third plurality of stacked memory dies, the fourth plurality of stacked memory dies, and the second dielectric material and the first plurality of stacked memory dies, the second plurality of stacked memory dies, and the first dielectric layer, respectively.

9 . The method of claim 7 , wherein providing the third plurality of semiconductor dies includes:
providing a plurality of semiconductor wafers each including a respective plurality of semiconductor dies; electrically coupling the plurality of semiconductor wafers to form a stack of semiconductor wafers; and dicing the stack of semiconductor wafers to create the third plurality of stacked semiconductor dies.

10 . The method of claim 9 , further comprising:
dicing the stack of semiconductor wafers to create multiple pluralities of stacked semiconductor dies; probing the multiple pluralities of stacked semiconductor dies to determine a quality of the multiple pluralities of stacked semiconductor dies; and selecting the third plurality of stacked semiconductor dies from the multiple pluralities of stacked semiconductor dies based on the quality.

11 . The method of claim 7 , wherein the first plurality of stacked semiconductor dies includes a first top memory die having first through-silicon vias (TSVs) and the second plurality of stacked semiconductor dies includes a second top memory die having second TSVs, the method further comprising:
disposing the first dielectric material at the first top memory die and the second top memory die such that an upper surface of the first dielectric material extends from the first top memory die and the second top memory die; and thinning the first dielectric material, the first top memory die, and the second top memory die to expose the first TSVs and the second TSVs.

12 . The method of claim 11 , further comprising:
forming first contact pads at the first TSVs; forming second contact pads at the second TSVs; coupling the third plurality of stacked semiconductor dies to the first contact pads; and coupling the fourth plurality of stacked semiconductor dies to the second contact pads.

13 . The method of claim 7 , further comprising:
dicing the wafer of logic dies, the first dielectric material, and the second dielectric material effective to create a first stacked semiconductor device assembly and a second stacked semiconductor device assembly, wherein the first stacked semiconductor device assembly includes a first logic die from the wafer of logic dies, the first plurality of stacked semiconductor dies, and the third plurality of stacked semiconductor dies, and wherein the second stacked semiconductor device assembly include

Assignees

• Micron Technology Inc

Inventors

• Bhushan Bharat
• Street Bret K
• Singh Akshay N
• Parekh Kunal R
• Zhou Wei

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/90 Primary

  Bond pads, in general · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title