Backside fuse structure utilizing backside contact

Patent metadata

Field	Value
Publication number	US-2025096127-A1
Application number	US-202318470664-A
Country	US
Kind code	A1
Filing date	Sep 20, 2023
Priority date	Sep 20, 2023
Publication date	Mar 20, 2025
Grant date	—

Abstract

A semiconductor integrated circuit (IC) device includes a backside fuse structure and a backside contact. The backside fuse structure is located within the backside of the semiconductor IC device vertically between a transistor there above and a backside back end of the line (BEOL) network. The backside fuse structure includes a fuse wire and a deep via contact that is connected to both the fuse wire and to a frontside BEOL network. The backside contact is connected to the transistor, to the backside BEOL network, and to the fuse wire. The backside fuse structure may be in a non-programmed state or a programmed state. When in a non-programmed state, an open circuit exists that prevents current flow through the fuse wire or through the backside contact.

First claim

What is claimed is:

1 . A semiconductor integrated circuit (IC) device comprising:
a fuse structure comprising a fuse wire and a deep via contact that is connected to the fuse wire and to a frontside back end of the line (BEOL) network; and a backside contact that is connected to a transistor, to a backside BEOL network, and to the fuse wire.

2 . The semiconductor IC device of claim 1 , wherein the fuse wire is between the deep via contact and the backside BEOL network.

3 . The semiconductor IC device of claim 1 , wherein a top surface of the fuse wire is connected to a bottom surface of the deep via contact.

4 . The semiconductor IC device of claim 1 , wherein a side surface of the fuse wire is connected to a sidewall of the backside contact.

5 . The semiconductor IC device of claim 1 , wherein a top surface of the backside contact is connected to a source/drain (S/D) region of the transistor.

6 . The semiconductor IC device of claim 1 , wherein, when the fuse structure is in a non-programmed state, the backside contact is a terminal for routing current through the transistor and for routing current between the frontside BEOL network and the backside BEOL network by way of the fuse wire.

7 . The semiconductor IC device of claim 1 , wherein, when the fuse structure is in a programmed state, an open circuit exists within the fuse wire that prevents the fuse wire from routing current between the frontside BEOL network and the backside BEOL network.

8 . The semiconductor IC device of claim 1 , wherein, when the fuse structure is in a programmed state, an open circuit exists within the backside contact that prevents the backside contact from routing current through the transistor and the backside contact from routing current between the frontside BEOL network and the backside BEOL network by way of the fuse wire.

9 . The semiconductor IC device of claim 1 , wherein a diffusion break region is between the transistor and the deep via contact.

10 . The semiconductor IC device of claim 1 , wherein the fuse wire is underneath a shallow trench isolation (STI) region.

11 . The semiconductor IC device of claim 1 , wherein the fuse wire is coplanar with a backside resistor wire.

12 . A semiconductor integrated circuit (IC) device method comprising:
programming a fuse structure that includes a fuse wire and a deep via contact, wherein the deep via contact is connected to the fuse wire and to a frontside back end of the line (BEOL) network, wherein the fuse wire is connected to a backside contact that is further connected to a transistor and to a backside BEOL network; and as a result of programming the fuse structure, preventing current flow between the frontside BEOL network and a backside BEOL network through the fuse wire.

13 . The semiconductor IC device method of claim 12 , wherein the fuse wire is between the deep via contact and the backside BEOL network.

14 . The semiconductor IC device method of claim 12 , wherein a top surface of the fuse wire is connected to a bottom surface of the deep via contact.

15 . The semiconductor IC device method of claim 12 , wherein a side surface of the fuse wire is connected to a sidewall of the backside contact.

16 . The semiconductor IC device method of claim 12 , wherein a top surface of the backside contact is connected to a source/drain (S/D) region of the transistor.

17 . A semiconductor integrated circuit (IC) device method comprising:
programming a fuse structure that includes a fuse wire and a deep via contact, wherein the deep via contact is connected to the fuse wire and to a frontside back end of the line (BEOL) network, wherein the fuse wire is connected to a backside contact that is further connected to a transistor and to a backside BEOL network; and as a result of programming the fuse structure, preventing the backside contact from routing current through the transistor and the backside contact from routing current between the frontside BEOL network and the backside BEOL network by way of the fuse wire.

18 . The semiconductor IC device method of claim 17 , wherein the fuse wire is between the deep via contact and the backside BEOL network.

19 . The semiconductor IC device method of claim 17 , wherein a top surface of the fuse wire is connected to a bottom surface of the deep via contact.

20 . The semiconductor IC device method of claim 17 , wherein a side surface of the fuse wire is connected to a sidewall of the backside contact.

Assignees

• IBM

Inventors

• Clevenger Lawrence A
• Moy Dan
• Haetty Jens
• Murphy Christopher
• Xie Ruilong
• Lanzillo Nicholas Anthony
• Huang Huai
• Shobha Hosadurga
• Jog Atharv

Classifications

• H10W20/493 Primary

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H01L23/5256 Primary

  Electricity · mapped topic