Backside fuse connected to backside back end of the line network

Patent metadata

Field	Value
Publication number	US-2025096126-A1
Application number	US-202318470655-A
Country	US
Kind code	A1
Filing date	Sep 20, 2023
Priority date	Sep 20, 2023
Publication date	Mar 20, 2025
Grant date	—

Abstract

A semiconductor integrated circuit (IC) device that includes a backside fuse structure. The backside fuse structure is located within the backside of the semiconductor IC device and may be vertically located between a microdevice and a backside back end of the line (BEOL) network. The backside fuse structure includes at least a fuse wire. The backside fuse structure may be in a non-programmed state or a programmed state. When in a non-programmed state, an open circuit exists that prevents current flow through the fuse wire. The backside fuse structure may be directly connected to a deep via contact and/or one or more conductive pathways within the backside BEOL network.

First claim

What is claimed is:

1 . A semiconductor integrated circuit (IC) device comprising:
a front end of line (FEOL) microdevice; a frontside back end of line (BEOL) network; a fuse structure comprising a deep via contact directly connected to a fuse wire and directly connected to the frontside BEOL network; a backside contact that is connected to the FEOL microdevice; and a backside BEOL network comprising a conductive pathway directly connected to the backside contact and directly connected to the fuse wire.

2 . The semiconductor IC device of claim 1 , wherein the fuse wire is vertically between the deep via contact and the backside BEOL network.

3 . The semiconductor IC device of claim 1 , wherein a top surface of the fuse wire is directly connected to a bottom surface of the deep via contact.

4 . The semiconductor IC device of claim 1 , wherein a bottom surface of the fuse wire is directly connected to the conductive pathway.

5 . The semiconductor IC device of claim 1 , wherein a bottom surface of the backside contact is directly connected to the conductive pathway.

6 . The semiconductor IC device of claim 1 , wherein, when the fuse structure is in a non-programmed state, the fuse wire enables the routing of current through the FEOL microdevice, through the backside BEOL network, and through the frontside BEOL network.

7 . The semiconductor IC device of claim 1 , wherein, when the fuse structure is in a programmed state, an open circuit exists within the fuse wire that prevents the fuse wire from routing current between the frontside BEOL network and the backside BEOL network.

8 . The semiconductor IC device of claim 1 , wherein the conductive pathway comprises a plurality of contact vias and one or more backside wires.

9 . The semiconductor IC device of claim 1 , wherein a bottom surface of the fuse wire is vertically below a bottom surface of the backside contact.

10 . The semiconductor IC device of claim 1 , wherein the fuse wire is below a shallow trench isolation (STI) region.

11 . The semiconductor IC device of claim 1 , wherein a top surface of the fuse wire is coplanar with a bottom surface of the backside contact.

12 . A semiconductor integrated circuit (IC) device comprising:
a front end of line (FEOL) microdevice; a backside contact that is connected to the FEOL microdevice; a fuse wire; and a backside BEOL network comprising a first conductive pathway directly connected to the backside contact and directly connected to the fuse wire and a second conductive pathway directly connected to the fuse wire.

13 . The semiconductor IC device of claim 12 , wherein the fuse wire is vertically between the backside contact and the backside BEOL network.

14 . The semiconductor IC device of claim 12 , wherein a bottom surface of the fuse wire is directly connected to the first conductive pathway.

15 . The semiconductor IC device of claim 12 , wherein a bottom surface of the fuse wire is directly connected to the second conductive pathway.

16 . The semiconductor IC device of claim 12 , wherein a bottom surface of the backside contact is directly connected to the first conductive pathway.

17 . The semiconductor IC device of claim 12 , wherein, when the fuse wire is in a non-programmed state, the fuse wire enables the routing of current through the FEOL microdevice, through the backside BEOL network between the first conductive pathway and the second conductive pathway.

18 . The semiconductor IC device of claim 12 , wherein, when the fuse wire is in a programmed state, an open circuit exists within the fuse wire that prevents the fuse wire from routing current between the first conductive pathway and the second conductive pathway.

19 . The semiconductor IC device of claim 12 , wherein a top surface of the fuse wire is coplanar with a bottom surface of the backside contact.

20 . A semiconductor integrated circuit (IC) device method comprising:
programming a fuse structure that comprises a fuse wire and a deep via contact, wherein the deep via contact is directly connected to the fuse wire and directly connected to a frontside back end of the line (BEOL) network, wherein the fuse wire is connected to a conductive pathway within a backside BEOL network; and as a result of programming the fuse structure, preventing current flow between the frontside BEOL network and the backside BEOL network through the fuse wire.

Assignees

• IBM

Inventors

• Moy Dan
• Haetty Jens
• Clevenger Lawrence A
• Yang Xiaoming
• Anderson Brent A
• Xie Ruilong
• Murphy Christopher

Classifications

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/083 Primary

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title