Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2025081864-A1
Application number	US-202418950227-A
Country	US
Kind code	A1
Filing date	Nov 18, 2024
Priority date	Mar 29, 2018
Publication date	Mar 6, 2025
Grant date	—

Abstract

A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the switching layer and the top electrode. The diffusion barrier structure includes a multiple-layer structure. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a bottom electrode; a top electrode, over the bottom electrode; a switching layer, between the bottom electrode and the top electrode, and configured to store data; a metal reservoir layer, between the switching layer and the top electrode; and a metal diffusion barrier layer, between the metal reservoir layer and the switching layer, wherein the metal diffusion barrier layer obstructs diffusion of metal ions from the metal reservoir layer to the switching layer.

2 . The semiconductor device of claim 1 , wherein a material of the metal diffusion barrier layer comprises metal, metal nitride or a combination thereof.

3 . The semiconductor device of claim 2 , wherein the metal comprises at least one of iridium (Ir), ruthenium (Ru), platinum (Pt), tantalum (Ta), titanium (Ti), titanium tungsten (TiW) and tungsten (W).

4 . The semiconductor device of claim 2 , wherein the metal nitride comprises at least one of titanium tungsten nitride (TiW(N)), titanium nitride (TiN) and tungsten nitride (WN).

5 . The semiconductor device of claim 1 , wherein a thickness of the metal diffusion barrier layer is between approximately 2 angstroms and approximately 25 angstroms.

6 . The semiconductor device of claim 1 , wherein the bottom electrode has a first portion and a second portion surrounding the first portion, and a thickness of the first portion is greater than a thickness of the second portion.

7 . A semiconductor device, comprising:
a bottom electrode; a top electrode, over the bottom electrode; a switching layer, between the bottom electrode and the top electrode, and configured to store data; a metal reservoir layer, between the switching layer and the top electrode; and a metal diffusion barrier layer, between the metal reservoir layer and the switching layer, wherein the metal diffusion barrier layer obstructs diffusion of metal ions from the metal reservoir layer to the switching layer, wherein the metal diffusion barrier layer has a first top surface and a second top surface surrounding the first top surface, and the first top surface is lower than the second top surface.

8 . The semiconductor device of claim 7 , wherein the metal diffusion barrier layer has a consistent thickness.

9 . The semiconductor device of claim 7 , wherein the bottom electrode has a first top surface and a second top surface surrounding the first top surface, and the first top surface is lower than the second top surface.

10 . The semiconductor device of claim 9 , wherein the bottom electrode has consistent thickness.

11 . The semiconductor device of claim 9 , wherein the first top surface of the metal diffusion barrier layer overlaps the first top surface of the bottom electrode.

12 . The semiconductor device of claim 7 , wherein switching layer has a first top surface and a second top surface surrounding the first top surface, and the first top surface is lower than the second top surface.

13 . The semiconductor device of claim 7 , wherein the metal reservoir layer has a first top surface and a second top surface surrounding the first top surface, and the first top surface is lower than the second top surface.

14 . The semiconductor device of claim 7 , wherein the top electrode has a first top surface and a second top surface surrounding the first top surface, and the first top surface is lower than the second top surface.

15 . The semiconductor device of claim 7 , further comprising:
a bottom metallization layer coupled to the bottom electrode; and a top metallization layer coupled to the top electrode.

16 . The semiconductor device of claim 15 , wherein the top metallization layer comprises a first portion and a second portion surrounding the first portion, and a thickness of the first portion is greater than a thickness of the second portion.

17 . A method for manufacturing semiconductor device, comprising:
forming a bottom electrode over a substrate; forming a switching layer over the bottom electrode; forming a metal diffusion barrier layer over the switching layer; forming a capping layer over the metal diffusion barrier layer; and forming a top electrode over the capping layer.

18 . The method of claim 17 , further comprising patterning the top electrode, the capping layer, the metal diffusion barrier layer, the switching layer and the bottom electrode such that a width of the bottom electrode is greater than a width of the capping layer, greater than a width of the metal diffusion barrier layer, and greater than a width of the top electrode.

19 . The method of claim 18 , wherein a width of the switching layer is equal to the width of the bottom electrode or less than the width of the bottom electrode.

20 . The method of claim 17 , further comprising forming a passivation layer over the bottom electrode.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Trinh Hai-Dang
• JIANG Fa-Shen
• Lin Hsing-Lien
• Wu Chii-Ming

Classifications

• H10N70/883

  Oxides or nitrides · CPC title

• H10N70/861

  Thermal details · CPC title

• H10N70/011

  Manufacture or treatment of multistable switching devices · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title