Semiconductor device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-2025081489-A1
Application number	US-202418601470-A
Country	US
Kind code	A1
Filing date	Mar 11, 2024
Priority date	Sep 6, 2023
Publication date	Mar 6, 2025
Grant date	—

Abstract

A semiconductor device includes a first electrode, a second electrode, a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. A concentration of the first impurity has a maximum value at a first position in a first direction inside the first semiconductor layer. The first direction is from the first electrode toward the second electrode. A concentration of proton is greater than the concentration of the first impurity in the second semiconductor layer. The concentration of the first impurity is greater than the concentration of proton in the third semiconductor layer. The concentration of the first impurity is greater than the concentration of proton in at least a portion of the first semiconductor layer at the second semiconductor layer side. The concentration of proton has a maximum value at a second position positioned at a side of the first position opposite to the first direction.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode, the first semiconductor layer including a first impurity and protons, the first impurity and the protons forming donors, the first semiconductor layer being of an n-conductivity type, a concentration of the first impurity having a maximum value at a first position in a first direction inside the first semiconductor layer, the first direction being from the first electrode toward the second electrode; a second semiconductor layer located at a first-direction side of the first semiconductor layer, the second semiconductor layer including the first impurity and protons, a concentration of proton being greater than the concentration of the first impurity in the second semiconductor layer, the second semiconductor layer being of the n-conductivity type; and a third semiconductor layer located at the first-direction side of the second semiconductor layer, the third semiconductor layer including the first impurity, the concentration of the first impurity being greater than the concentration of proton in the third semiconductor layer, the third semiconductor layer being of the n-conductivity type, the concentration of the first impurity being greater than the concentration of proton in at least a portion of the first semiconductor layer at the second semiconductor layer side, the concentration of proton having a maximum value at a second position in the first direction, the second position being positioned at a side of the first position opposite to the first direction.

2 . The device according to claim 1 , wherein
the second s positioned inside the first semiconductor layer.

3 . The device according to claim 1 , wherein
the second position is positioned at a surface of the first semiconductor layer at the first electrode side.

4 . The device according to claim 1 , further comprising:
a fourth semiconductor layer of a p-conductivity type provided between the first electrode and the first semiconductor layer, the first semiconductor layer being positioned at the first-direction side of the fourth semiconductor layer.

5 . The device according to claim 4 , wherein
the second position is positioned inside the fourth semiconductor layer.

6 . The device according to claim 4 , wherein
the second position is positioned at a surface of the fourth semiconductor layer at a side opposite to the first semiconductor layer.

7 . The device according to claim 4 , further comprising:
a fifth semiconductor layer located at the first-direction side of the third semiconductor layer, the fifth semiconductor layer being of the p-conductivity type.

8 . The device according to claim 7 , further comprising:
a sixth semiconductor layer located at the first-direction side of the fifth semiconductor layer, the sixth semiconductor layer being of the n-conductivity type; a gate electrode facing the fifth semiconductor layer; and a gate insulating film located between the fifth semiconductor layer and the gate electrode, the first electrode being a collector electrode connected to the fourth semiconductor layer, the second electrode being an emitter electrode connected to the sixth semiconductor layer.

9 . The device according to claim 1 , wherein
the first impurity is phosphorus.

10 . A method for manufacturing a semiconductor device, the method comprising:
implanting a first impurity into a semiconductor member in a first direction from a first surface side of the semiconductor member so that a first impurity concentration has a maximum value at a first position in the first direction inside the semiconductor member, the first impurity forming donors, the semiconductor member being of an n-conductivity type; providing an absorber at the first surface side of the semiconductor member; implanting protons into the semiconductor member in the first direction via the absorber so that a concentration of proton has a maximum value at a second position in the first direction, the second position being positioned at a side of the first position opposite to the first direction; and removing the absorber.

11 . The method according to claim 10 , wherein
a target position of the second position in the first direction is set to be the first surface in the implanting of the protons.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Hayashi Masato
• Naijo Tatsuo

Classifications

• H10D62/60

  Impurity distributions or concentrations · CPC title

• H10D12/418

  having a drift region having a doping concentration that is higher at the emitter side relative to other parts of the drift region · CPC title

• H10D12/417

  having a drift region having a doping concentration that is higher at the collector side relative to other parts of the drift region · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title