Switch fet body current management devices and methods

US2025080104A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025080104-A1
Application numberUS-202418952576-A
CountryUS
Kind codeA1
Filing dateNov 19, 2024
Priority dateJul 31, 2020
Publication dateMar 6, 2025
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Methods and devices to reduce gate induced drain leakage current in RF switch stacks are disclosed. The described devices utilize multiple discharge paths and/or less negative body bias voltages without compromising non-linear performance and power handling capability of power switches. Moreover, more compact bias voltage generation circuits with smaller footprint can be implemented as part of the disclosed devices.

First claim

Opening claim text (preview).

What is claimed is: 1 . A field effect transistor (FET) switch stack comprising: serially connected FETs coupled at one end to a first terminal and at another end to a second terminal, the first terminal being configured to receive a radio frequency (RF) signal; a body resistor ladder coupled to the first terminal, the body resistor ladder comprising a plurality of body resistor elements connected in series, each body resistor element coupled across body terminals of corresponding adjacent FETs of the serially connected FETs; and a first diode element arrangement comprising: i) a diode element stack comprising two or more diode elements, the diode element stack coupled between the body resistor ladder and the first terminal, and ii) one or more additional diode elements, coupled to the body resistor ladder.

Assignees

Inventors

Classifications

  • H03K17/693Primary

    Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

  • Special modifications or use of the back gate voltage of a FET · CPC title

  • Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

  • H03K17/162Primary

    without feedback from the output circuit to the control circuit · CPC title

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What does patent US2025080104A1 cover?
Methods and devices to reduce gate induced drain leakage current in RF switch stacks are disclosed. The described devices utilize multiple discharge paths and/or less negative body bias voltages without compromising non-linear performance and power handling capability of power switches. Moreover, more compact bias voltage generation circuits with smaller footprint can be implemented as part of …
Who is the assignee on this patent?
Psemi Corp
What technology area does this patent fall under?
Primary CPC classification H03K17/693. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Mar 06 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).