Semiconductor package

Patent metadata

Field	Value
Publication number	US-2025079403-A1
Application number	US-202418666556-A
Country	US
Kind code	A1
Filing date	May 16, 2024
Priority date	Aug 29, 2023
Publication date	Mar 6, 2025
Grant date	—

Abstract

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, the first semiconductor substrate including an active surface and an inactive surface opposite to each other, a plurality of second semiconductor chips stacked on the first semiconductor chip, each of the plurality of second semiconductor chips including a second semiconductor substrate including an active surface and an inactive surface opposite to each other, a plurality of conductive patterns on the active surface of each second semiconductor substrate of the plurality of second semiconductor chips, and a plurality of bonding pads on the inactive surface of the first semiconductor substrate and on the inactive surface of each second semiconductor substrate of the plurality of second semiconductor chips, where the plurality of bonding pads are respectively connected to the plurality of conductive patterns.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a first semiconductor chip comprising a first semiconductor substrate, the first semiconductor substrate comprising an active surface and an inactive surface opposite to each other; a plurality of second semiconductor chips stacked on the first semiconductor chip, each of the plurality of second semiconductor chips comprising a second semiconductor substrate comprising an active surface and an inactive surface opposite to each other; a plurality of conductive patterns on the active surface of the second semiconductor substrate of each of the plurality of second semiconductor chips; and a plurality of bonding pads on the inactive surface of the first semiconductor substrate and on the inactive surface of the second semiconductor substrate of each of the plurality of second semiconductor chips, wherein the plurality of bonding pads are respectively connected to the plurality of conductive patterns, wherein each of the plurality of conductive patterns comprises:
an inner conductive pattern; and
an outer conductive pattern comprising a portion between the inner conductive pattern and a respective bonding pad,
wherein the outer conductive pattern comprises a first metal that is ionized into an N-valent cation, N being a natural number of 1 or more, and wherein a reduction potential of the first metal ionized into the N-valent cation is in a range from (−10×N) V to (−0.1567×N) V.

2 . The semiconductor package of claim 1 ,
wherein the reduction potential of the first metal ionized into the N-valent cation is greater than (−0.9567V×N) V.

3 . The semiconductor package of claim 1 , wherein the inner conductive pattern comprises a first material, the outer conductive pattern comprises a second material, and the bonding pad comprises a third material, and
wherein the first material, the second material and the third material have different reduction potentials.

4 . The semiconductor package of claim 1 , wherein the inner conductive pattern comprises aluminum.

5 . The semiconductor package of claim 1 , wherein the bonding pad comprises copper.

6 . The semiconductor package of claim 1 , wherein the outer conductive pattern comprises Ti, V, or a combination thereof.

7 . The semiconductor package of claim 1 , wherein a horizontal width of each of the plurality of conductive patterns decreases from an upper side to a lower side.

8 . The semiconductor package of claim 1 , wherein a horizontal width of each of the plurality of conductive patterns is different with respect to a horizontal width of each of the plurality of bonding pads, such that sidewalls of the plurality of bonding pads are within the horizontal width of respective conductive patterns of the plurality of conductive patterns.

9 . The semiconductor package of claim 1 , wherein the outer conductive pattern conformally covers a lower surface and a sidewall of the inner conductive pattern.

10 . The semiconductor package of claim 1 , further comprising:
a plurality of bonding insulating layers at least partially surrounding the plurality of bonding pads; and a plurality of wiring layers at least partially surrounding the plurality of conductive patterns, wherein each of the plurality of wiring layers comprises an upper wiring layer and a lower wiring layer, and wherein the upper wiring layer comprises a material different from a material of the lower wiring layer.

11 . The semiconductor package of claim 10 , wherein each upper wiring layer covers at least a portion of sidewalls of the plurality of bonding pads and at least a portion of sidewalls of the plurality of conductive patterns, and
wherein each lower wiring layer is spaced apart from the sidewalls of the plurality of conductive patterns.

12 . The semiconductor package of claim 1 , wherein the reduction potential of the first metal ionized into the N-valent cation is equal to or lower than (−0.5567×N) V.

13 . A semiconductor package comprising:
a first semiconductor chip comprising a first semiconductor substrate and a plurality of first through electrodes extending through the first semiconductor substrate, the first semiconductor substrate comprising an active surface and an inactive surface opposite to each other; a plurality of second semiconductor chips stacked on the first semiconductor chip, each of the plurality of second semiconductor chips comprising a second semiconductor substrate and a plurality of second through electrodes extending through the second semiconductor substrate comprising an active surface and an inactive surface opposite to each other; a plurality of conductive patterns on the active surface of the second semiconductor substrate of each of the plurality of second semiconductor chips; and a plurality of bonding pads on the plurality of first through electrodes and the plurality of second through electrodes, wherein the plurality of bonding pads are respectively electrically connected between the plurality of first through electrodes and the plurality of conductive patterns, and between the plurality of second through electrodes and the plurality of conductive patterns, wherein each of the plurality of conductive patterns comprises a first metal that is ionized into an N-valent cation, N being a natural number of 1 or more, and wherein a reduction potential of the first metal ionized into the N-valent cation is in a range from (−0.9567×N) V to (−0.1567×N) V.

14 . The semiconductor package of claim 12 , wherein the reduction potential of the first metal ionized into the N-valent cation is equal to or lower than (−0.5567×N) V.

15 . The semiconductor package of claim 12 , wherein the outer conductive pattern comprises Ti, V, Zn, or a combination thereof.

16 . The semiconductor package of claim 12 , wherein a horizontal width of each of the plurality of conductive patterns is different with respect to a horizontal width of each of the plurality of bonding pads, such that sidewalls of the plurality of bonding pads are within the horizontal width of respective conductive patterns of the plurality of conductive patterns.

17 . A semiconductor package comprising:
a first semiconductor chip comprising a first semiconductor substrate and a plurality of first through electrodes extending through the first semiconductor substrate, the first semiconductor substrate comprising an active surface and an inactive surface opposite to each other; a plurality of second semiconductor chips stacked on the first semiconductor chip, each of the plurality of second semiconductor chips comprising a second semiconductor substrate and a plurality of second through electrodes extending through the second semiconductor substrate, wherein the second semiconductor substrate of each of the plurality of second semiconductor chips comprises an active surface and an inactive surface opposite to each other; a plurality of conductive patterns on the active surface of the second semiconductor substrate of each of the plurality of seconds semiconductor chips, the plurality of conductive patterns comprising aluminum; and a plurality of bonding pads on the inactive surface of the first semiconductor substrate and the inactive surface of the second semiconductor substrate of each of the plurality of second semiconductor chips, wherein the plurality of bonding pads are respectively connected to the plurality of conductive patterns, wherein each of the plurality of conductive patterns comprises:
an inner conductive pattern comprising copper; and
an outer conductive p

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lin Jing Cheng
• Jee Youngkun

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title