Semiconductor package for increasing bonding reliability

Patent metadata

Field	Value
Publication number	US-2025079365-A1
Application number	US-202418667796-A
Country	US
Kind code	A1
Filing date	May 17, 2024
Priority date	Aug 28, 2023
Publication date	Mar 6, 2025
Grant date	—

Abstract

A semiconductor package includes a first semiconductor chip and a second semiconductor chip hybrid-bonded to the first semiconductor chip. The first semiconductor chip includes first main pads, which are apart from each other, and a first bonding insulation layer extending around the first main pads. Each of the first main pads includes first sub main pads apart from each other. The second semiconductor chip includes second main pads, which are spaced apart from each other, and a second bonding insulation layer extending around the second main pads. The second main pads are aligned with the first main pads. Each of the second main pads includes second sub main pads spaced apart from each other. Each of the second sub main pads is bonded to a respective one of the first sub main pads. The second bonding insulation layer is bonded to the first bonding insulation layer.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a first semiconductor chip; and a second semiconductor chip hybrid-bonded to the first semiconductor chip, wherein the first semiconductor chip comprises a plurality of first main pads and a first bonding insulation layer extending around the plurality of first main pads, wherein the plurality of first main pads are spaced apart from each other, and wherein each of the plurality of first main pads comprises a plurality of first sub main pads spaced apart from each other, wherein the second semiconductor chip comprises a plurality of second main pads and a second bonding insulation layer extending around the plurality of second main pads, wherein the plurality of second main pads are spaced apart from each other, and wherein the plurality of second main pads are aligned with the plurality of first main pads, wherein each of the plurality of second main pads comprises a plurality of second sub main pads spaced apart from each other, wherein each of the plurality of second sub main pads is bonded to a respective one of the plurality of first sub main pads, and wherein the second bonding insulation layer is bonded to the first bonding insulation layer.

2 . The semiconductor package of claim 1 , wherein a top surface of each of the plurality of first main pads is coplanar with a top surface of the first bonding insulation layer, and wherein a bottom surface of each of the plurality of second main pads is coplanar with a bottom surface of the second bonding insulation layer.

3 . The semiconductor package of claim 1 , wherein the first bonding insulation layer is between the plurality of first sub main pads, and the second bonding insulation layer is between the plurality of second sub main pads.

4 . The semiconductor package of claim 1 , wherein each of the plurality of first main pads is divided by the first bonding insulation layer into the plurality of first sub main pads, and each of the plurality of second main pads is divided by the second bonding insulation layer into the plurality of second sub main pads.

5 . The semiconductor package of claim 1 , wherein each of the first bonding insulation layer and the second bonding insulation layer comprises a silicon oxide layer or a silicon nitride layer.

6 . The semiconductor package of claim 1 , wherein a thickness of each of the plurality of second sub main pads is less than a thickness of each of the plurality of first sub main pads.

7 . The semiconductor package of claim 1 , wherein a width of each of the plurality of second sub main pads is equal to a width of each of the plurality of first sub main pads.

8 . The semiconductor package of claim 1 , wherein each of the plurality of second sub main pads is bonded to a respective one of the plurality of first sub main pads at a respective bonding region, and wherein the second bonding insulation layer is bonded to the first bonding insulation layer at an insulating bonding region.

9 . The semiconductor package of claim 1 , wherein the plurality of first main pads are in a first main pad region located in a central region of the first semiconductor chip in a plan view, and the plurality of second main pads are in a second main pad region located in a central region of the second semiconductor chip in the plan view.

10 . The semiconductor package of claim 9 , wherein the first semiconductor chip further comprises a first dummy pad region in a peripheral region that extends around the first main pad region, wherein the first dummy pad region comprises first dummy pads arranged therein, and
wherein the second semiconductor chip further comprises a second dummy pad region in a peripheral region that extends around the second main pad region, wherein the second dummy pad region comprises second dummy pads arranged therein.

11 . A semiconductor package comprising:
a first semiconductor chip; and a second semiconductor chip hybrid-bonded to the first semiconductor chip, wherein the first semiconductor chip comprises a plurality of first main pads, a first bonding insulation layer extending around the plurality of first main pads, and a support pad, wherein the plurality of first main pads are spaced apart from each other, wherein each of the plurality of first main pads comprises a plurality of first sub main pads spaced apart from each other, and wherein the plurality of first sub main pads are on the support pad, wherein the second semiconductor chip comprises a plurality of second main pads and a second bonding insulation layer extending around the plurality of second main pads, wherein the plurality of second main pads are spaced apart from each other, wherein each of the plurality of second main pads comprises a plurality of second sub main pads spaced apart from each other, wherein the second semiconductor chip further comprises a support via, and wherein the plurality of second sub main pads are on the support via, wherein each of the plurality of second sub main pads is bonded to a respective one of the plurality of first sub main pads, and wherein the second bonding insulation layer is bonded to the first bonding insulation layer.

12 . The semiconductor package of claim 11 , wherein the first bonding insulation layer is between the plurality of first sub main pads, and wherein the support pad is spaced apart from the first bonding insulation layer.

13 . The semiconductor package of claim 11 , wherein the second bonding insulation layer is between the plurality of second sub main pads, and wherein the support via is on the second bonding insulation layer and the plurality of second sub main pads.

14 . The semiconductor package of claim 11 , wherein a width of the support pad is greater than a width of each of the plurality of first main pads.

15 . The semiconductor package of claim 11 , wherein a width of the support via is greater than a width of each of the plurality of second sub main pads.

16 . A semiconductor package comprising:
a first semiconductor chip; and a second semiconductor chip hybrid-bonded to the first semiconductor chip, wherein the first semiconductor chip comprises a first substrate structure, a plurality of first main pads on the first substrate structure, and a first bonding insulation structure extending around the plurality of first main pads, wherein the first substrate structure comprises a support pad, and wherein the plurality of first main pads are spaced apart from each other, wherein each of the plurality of first main pads comprises a plurality of first sub main pads spaced apart from each other, and wherein the plurality of first sub main pads are supported by the support pad, wherein the second semiconductor chip comprises a second substrate structure, a plurality of second main pads spaced apart from each other, and a second bonding insulation structure extending around the plurality of second main pads, and wherein the second substrate structure comprises a support via, wherein each of the plurality of second main pads includes a plurality of second sub main pads spaced apart from each other, wherein the plurality of second sub main pads are supported by the support via, wherein each of the plurality of second sub main pads is bonded to a respective one of the plurality of first sub main pads, and wherein the second bonding insulation structure is bonded to the first bonding insulation structure.

17 . The semiconductor package of claim 16 , wherein the first substrate structure further comprises a wiring layer, and wherein the support pad is in the w

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lin Jing Cheng
• Jee Youngkun

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W72/967

  Multiple bond pads having different functions · CPC title

• H10W72/951

  Materials of bond pads · CPC title

• H10W72/921

  Structures or relative sizes of bond pads · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title