Hybrid metal line structure

Patent metadata

Field	Value
Publication number	US-2025079298-A1
Application number	US-202418952043-A
Country	US
Kind code	A1
Filing date	Nov 19, 2024
Priority date	Mar 25, 2021
Publication date	Mar 6, 2025
Grant date	—

Abstract

The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.

First claim

What is claimed is:

1 . An integrated chip comprising:
a substrate; a dielectric layer over the substrate; and a hybrid metal line on the dielectric layer, the hybrid metal line comprising:
a first metal line and a second metal line comprising a first metal; and
a third metal line comprising a second metal, different than the first metal, extending from a sidewall of the first metal line to a sidewall of the second metal line,
wherein a bottom surface of the first metal line, a bottom surface of the second metal line, and a bottom surface of the third metal line are on the dielectric layer.

2 . The integrated chip of claim 1 , further comprising:
a fourth metal line comprising the first metal on the dielectric layer and laterally spaced from the hybrid metal line.

3 . The integrated chip of claim 1 , wherein a first conductive interconnect is on the hybrid metal line, and wherein the hybrid metal line is on a second conductive interconnect.

4 . The integrated chip of claim 1 , wherein the bottom surface of the third metal line extends along the dielectric layer from the bottom surface of the first metal line to the bottom surface of the second metal line.

5 . The integrated chip of claim 1 , wherein the bottom surface of the first metal line, the bottom surface of the second metal line, and the bottom surface of the third metal line are on a top surface of the dielectric layer.

6 . The integrated chip of claim 1 , wherein the bottom surface of the first metal line, the bottom surface of the second metal line, and the bottom surface of the third metal line directly contact the dielectric layer.

7 . The integrated chip of claim 1 , wherein the bottom surface of the first metal line has a first width, the bottom surface of the second metal line has a second width, different than the first width, and the bottom surface of the third metal line has a third width, different than the first width and the second width.

8 . The integrated chip of claim 1 , the hybrid metal line further comprising:
a fourth metal line and a fifth metal line on opposite sides of the third metal line and coupled to the third metal line, wherein the first metal line is between the fourth metal line and the third metal line, wherein the second metal line is between the fifth metal line and the third metal line, and wherein a bottom surface of the fourth metal line and a bottom surface of the fifth metal line are on the dielectric layer.

9 . The integrated chip of claim 1 , wherein a resistivity of the second metal is less than a resistivity of the first metal.

10 . The integrated chip of claim 1 , wherein the second metal is spaced over the dielectric layer.

11 . An integrated chip comprising:
a substrate; a first metal line over the substrate, the first metal line comprising a first metal; and a hybrid metal line over the substrate and laterally spaced from the first metal line, the hybrid metal line comprising:
a second metal line and a third metal line comprising the first metal; and
a fourth metal line comprising a second metal, different than the first metal, between and coupled to the second metal line and the third metal line,
wherein a bottom surface of the second metal line and a bottom surface of the third metal line are above a bottom surface of the fourth metal line.

12 . The integrated chip of claim 11 , further comprising:
a first dielectric layer over the substrate, wherein the bottom surface of the fourth metal line is on the first dielectric layer; and a second dielectric layer on the first dielectric layer and between the first metal line and the second metal line, wherein the bottom surface of the second metal line is above a bottom surface of the second dielectric layer.

13 . The integrated chip of claim 11 , further comprising:
a dielectric layer over the substrate, wherein the bottom surface of the fourth metal line is on the dielectric layer, and wherein the bottom surface of the second metal line and the bottom surface of the third metal line are spaced over the dielectric layer.

14 . The integrated chip of claim 11 , further comprising:
an adhesion layer under the bottom surface of the second metal line and the bottom surface of the third metal line.

15 . The integrated chip of claim 14 , wherein the fourth metal line is directly between a first bottom surface of the adhesion layer and a second bottom surface of the adhesion layer.

16 . A method for forming an interconnect structure, the method comprising:
depositing a first metal layer over a substrate; etching the first metal layer to form a first opening in the first metal layer; depositing a second metal layer different than the first metal layer in the first opening to form a first metal line from the second metal layer between sidewalls of the first metal layer; etching the first metal layer on a first side of the first metal line to form a second metal line and a third metal line from the first metal layer on the first side of the first metal line, the second metal line coupled to the first metal line, the third metal line laterally spaced from the second metal line; and depositing a first dielectric layer between the second metal line and the third metal line.

17 . The method of claim 16 , further comprising:
etching the first metal layer on a second side of the first metal line to form a fourth metal line and a fifth metal line from the first metal layer on the first side of the first metal line, the fourth metal line contacting the first metal line, the fifth metal line laterally spaced from the second metal line; and depositing the first dielectric layer between the fourth metal line and the fifth metal line.

18 . The method of claim 16 , further comprising:
depositing a second dielectric layer over the substrate, wherein the first metal layer is deposited on the second dielectric layer, wherein the etching of the first metal layer to form the first opening in the first metal layer uncovers a portion of the second dielectric layer, and wherein the second metal layer is deposited on the portion of the second dielectric layer.

19 . The method of claim 16 , further comprising:
performing a planarization process of the first metal line and the first metal layer before the etching of the first metal layer on the first side of the first metal line.

20 . The method of claim 16 , wherein a sidewall of the second metal line is in contact with a sidewall of the first metal line.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ho Pokuan
• Wu Chia-Tien
• Chen Hsin-Ping
• Chu Wei-Chen

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title