Memory device and manufacturing method of the memory device

Patent metadata

Field	Value
Publication number	US-2025071995-A1
Application number	US-202418943125-A
Country	US
Kind code	A1
Filing date	Nov 11, 2024
Priority date	Feb 24, 2021
Publication date	Feb 27, 2025
Grant date	—

Abstract

There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate stack structure and a second gate stack structure, disposed on a substrate; and a slit disposed between the first gate stack structure and the second gate stack structure to electrically isolate the first gate stack structure and the second gate stack structure from each other.

First claim

What is claimed is:

1 . A method of manufacturing a memory device, the method comprising:
forming a stack structure by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate including a first memory region, a second memory region, and a slit region between the first memory region and the second memory region; forming a plurality of first holes penetrating the stack structure within the slit region and second holes penetrating the stack structure within the first memory region and the second memory region; forming cell plugs in the second holes; forming plate electrode layers by filling a conductive layer in a space in which the sacrificial layer is removed, after the sacrificial layer exposed through internal sidewalls of the first holes is removed; and electrically isolating the plate electrode layers disposed within the first memory region and the plate electrode layers disposed within the second memory region from each other by etching the plate electrodes exposed through the first holes.

2 . The method of claim 1 , wherein the plurality of first holes are arranged in a line within the slit region, or are arranged in a zigzag shape within the slit region.

3 . The method of claim 1 , further comprising forming a mask pattern which shields openings of the first holes on a top of the stack structure within the slit region, before the forming of the cell plugs in the second holes.

4 . The method of claim 1 , wherein, in the electrically isolating of the plate electrodes from each other, one end portions of the plate electrode layers disposed within the first memory region, which are adjacent to the first holes, are etched to have a first wave pattern, and one end portions of the plate electrode layers disposed within the second memory region, which are adjacent to the first holes, are etched to have a second wave pattern.

5 . The method of claim 4 , wherein the first wave pattern and the second wave pattern are substantially symmetrical to each other.

6 . The method of claim 1 , wherein, in the electrically isolating of the plate electrode layers from each other, the plate electrode layers formed within the slit region are etched and removed such that the first holes are connected to each other.

7 . The method of claim 1 , further comprising:
forming capping patterns in spaces in which the plate electrode layers are etched, after the electrically isolating of the plate electrode layers from each other; and forming a source line contact at the inside of the slit.

8 . A method of manufacturing a memory device, the method comprising:
forming a stack structure by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate including a first memory region, a second memory region, and a slit region between the first memory region and the second memory region; forming a plurality of holes penetrating the stack structure within the slit region; removing the sacrificial layers through the plurality of holes; forming plate electrode layers by filling a conductive layer in spaces in which the sacrificial layers are removed; and removing the plate electrode layers formed within the slit region through the plurality of holes.

9 . The method of claim 8 , wherein, in the removing of the plate electrode layers, the plate electrode layers formed within the first memory region and the plate electrode layers formed within the second memory region are electrically and physically isolated from each other.

10 . The method of claim 8 , wherein, in the removing of the plate electrode layers, the plate electrode layers formed within the slit region are etched and removed such that the holes are connected to each other.

11 . The method of claim 8 , wherein, in the removing of the plate electrode layers, one end portions of the plate electrode layers disposed within the first memory region, which are adjacent to the holes, are etched to have a first wave pattern, and one end portions of the plate electrode layers disposed within the second memory region, which are adjacent to the holes, are etched to have a second wave pattern.

12 . The method of claim 11 , wherein the first wave pattern and the second wave pattern are substantially symmetrical to each other.

Assignees

• Sk Hynix Inc

Inventors

• Choi Won Geun
• Jang Jung Shik
• Kim Jang Won
• Park Mi Seong

Classifications

• H10W10/20

  Air gaps · CPC title

• H10W10/021

  of air gaps · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title