Phase-locked loop circuit, phase error sign generator and rfic

Patent metadata

Field	Value
Publication number	US-2025070790-A1
Application number	US-202418808348-A
Country	US
Kind code	A1
Filing date	Aug 19, 2024
Priority date	Aug 22, 2023
Publication date	Feb 27, 2025
Grant date	—

Abstract

A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock signal of the PLL circuit, a phase detector configured to generate a phase error signal representing a phase difference between a first clock signal based on a reference clock signal and a second clock signal based on the output clock signal, a comparator configured to generate a phase error sign signal based on a reference voltage and the phase error signal, and a reference voltage generation circuit configured to scale first and second sign values of the phase error sign signal based on a fixed gain value and a variable gain value, respectively, and generate the reference voltage based on the scaled first and second sign values.

First claim

What is claimed is:

1 . A phase-locked loop (PLL) circuit comprising:
a voltage-controlled oscillator configured to generate an output clock signal of the PLL circuit; a phase detector configured to generate a phase error signal representing a phase difference between a first clock signal based on a reference clock signal, and a second clock signal based on the output clock signal; a comparator configured to generate a phase error sign signal based on a reference voltage and the phase error signal; and a reference voltage generation circuit configured to scale first and second sign values of the phase error sign signal based on a fixed gain value and a variable gain value, respectively, and generate the reference voltage based on the scaled first and second sign values.

2 . The PLL circuit of claim 1 , wherein the reference voltage generation circuit adjusts the variable gain value such that an average value of the first and second sign values of the phase error sign signal is zero when the PLL circuit is in a locked state.

3 . The PLL circuit of claim 1 , wherein the reference voltage generation circuit comprises:
a scaling circuit configured to scale the two sign values of the phase error sign signal by the fixed gain value and the variable gain value, respectively; a delta-sigma modulator configured to output a 2-bit signal based on the scaled two sign values; and a digital-to-analog converter (DAC) configured to generate the reference voltage based on the 2-bit signal.

4 . The PLL circuit of claim 3 , wherein the DAC is a delta-voltage DAC comprising an output capacitor charged, held, or discharged by one step based on the 2-bit signal and configured to output the reference voltage.

5 . The PLL circuit of claim 4 , wherein:
the 2-bit signal comprises an up-signal to increase the reference voltage, a down-signal to decrease the reference voltage, and a hold signal to hold the reference voltage, and up-current flowing through the output capacitor based on the up-signal and down-current flowing through the output capacitor based on the down-signal have different magnitudes.

6 . The PLL circuit of claim 5 , wherein:
the first sign value of the phase error sign signal corresponds to a positive number and the second sign value corresponds to a negative number, and the delta-sigma modulator generates the 2-bit signal based on the first sign value scaled by the variable gain value and the second sign value scaled by the fixed gain value.

7 . The PLL circuit of claim 5 , wherein the reference voltage generation circuit increases the variable gain value when the down-current is larger than the up-current and decreases the variable gain value when the up-current is larger than the down-current.

8 . The PLL circuit of claim 5 , wherein:
the first sign value of the phase error sign signal corresponds to a positive number and the second sign value corresponds to a negative number, and the delta-sigma modulator generates the 2-bit signal based on the first sign value scaled by the fixed gain value and the second sign value scaled by the variable gain value.

9 . The PLL circuit of claim 5 , wherein the reference voltage generation circuit decreases the variable gain value when the down-current is larger than the up-current and increases the variable gain value when the up-current is larger than the down-current.

10 . The PLL circuit of claim 1 , wherein the reference voltage generation circuit adjusts the variable gain value based on an integral value of the phase error sign signal.

11 . The PLL circuit of claim 3 , wherein:
the scaling circuit comprises:
a multiplexer configured to output a first constant corresponding to the first sign value and a second constant corresponding to the second sign value based on two code values of the phase error sign signal;
an integrator configured to integrate an output of the multiplexer; and
a quantizer configured to quantize the integral value of the integrator to generate the variable gain value, and
the first and second constants have the same absolute value less than 1 but with opposite signs.

12 . The PLL circuit of claim 1 , comprising:
a digital-to-time converter (DTC) configured to delay the reference clock signal based on a DTC code; a control code generation circuit configured to generate a division ratio code and the DTC code based on a frequency control word (FCW) and the phase error sign signal; and a divider configured to generate a feedback clock signal based on the division ratio code and the output clock signal, wherein, the first clock signal is the reference clock signal delayed by the DTC, and the second clock signal is the feedback clock signal.

13 . The PLL circuit of claim 12 , wherein the control code generation circuit comprises:
a delta-sigma modulator configured to generate the division ratio code based on the FCW; an integrator configured to integrate a difference between the division ratio code and the FCW to generate a phase error code; and a DTC calibration circuit configured to generate the DTC code based on the phase error code and the phase error sign signal.

14 . The PLL circuit of claim 13 , wherein the DTC calibration circuit comprises a DTC nonlinearity calibration circuit configured to generate an offset value for calibrating nonlinearity of the DTC based on the phase error sign signal and the phase error code.

15 . The PLL circuit of claim 13 , wherein the DTC calibration circuit comprises a DTC gain calibration circuit configured to generate a DTC gain value for scaling the phase error code based on the phase error sign signal and the phase error code.

16 . The PLL circuit of claim 12 , wherein the phase error signal is a sampled voltage signal, and the PLL circuit further comprising:
a transconductance circuit configured to convert a difference between the phase error signal and a reference signal into a current signal; and a loop filter configured to convert the converted current signal into a voltage signal for controlling an operation of the voltage-controlled oscillator, wherein the reference voltage generation circuit generates the reference voltage such that a threshold voltage of the comparator tracks a threshold voltage of the transconductance circuit when the PLL circuit is in a locked state.

17 . A phase error sign generator comprising:
a comparator configured to generate a phase error sign signal based on a reference voltage and a phase error signal; and a reference voltage generation circuit configured to scale first and second sign values of the phase error sign signal based on a fixed gain value and a variable gain value, respectively, and generate the reference voltage based on the scaled first and second sign values.

18 . The phase error sign generator of claim 17 , wherein the reference voltage generation circuit adjusts the variable gain value such that an average value of the first and second sign values of the phase error sign signal is zero.

19 . The phase error sign generator of claim 17 , wherein the phase error signal is an output signal of a sampling phase detector within a phase-locked loop (PLL).

20 . A radio-frequency integrated circuit (RFIC) comprising:
a mixer; and a local oscillator configured to provide a reference frequency source to the mixer, wherein the local oscillator comprises:
a voltage-controlled oscillator configured to generate an output clock signal;
a phase detector configured to generate a phase error signal re

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Minseob
• Yoo Sangmin
• Lee Joonhee
• Jo Ikkyun
• Han Honggul

Classifications

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/097

  using a comparator for comparing the voltages obtained from two frequency to voltage converters · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/081

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H03L7/0805

  the loop being adapted to provide an additional control signal for use outside the loop · CPC title