Semiconductor package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2025070039-A1
Application number	US-202418632486-A
Country	US
Kind code	A1
Filing date	Apr 11, 2024
Priority date	Aug 22, 2023
Publication date	Feb 27, 2025
Grant date	—

Abstract

A semiconductor package includes a package substrate and at least two semiconductor chips stacked on the package substrate and electrically connected to the package substrate via a wire, in which a first semiconductor chip located on a lower side among the at least two semiconductor chips is coupled, without an adhesive, to a second semiconductor chip located above the first semiconductor chip.

First claim

1 . A semiconductor package comprising:
a package substrate; and at least two semiconductor chips stacked on the package substrate and electrically connected to the package substrate via a wire, wherein a first semiconductor chip located on a lower side among the at least two semiconductor chips is coupled, without an adhesive, to a second semiconductor chip located above the first semiconductor chip.

2 . The semiconductor package of claim 1 , wherein:
each of the at least two semiconductor chips has an upper surface and a lower surface having rectangular shapes, and the upper surface comprises an active surface and the lower surface comprises a non-active surface, chip pads are arranged in a first direction on the upper surface of each of the at least two semiconductor chips, the chip pads are adjacent to a first edge that corresponds to one line of the rectangular shapes of the upper and lower surfaces of each of the at least two semiconductor chips and extend in the first direction, an alignment pattern line is formed on the upper surface of the first semiconductor chip and extends parallel to the first edge of the upper surface of the first semiconductor chip, and the first edge of the lower surface of the second semiconductor chip is self-aligned with the alignment pattern line of the first semiconductor chip.

3 . The semiconductor package of claim 2 , wherein the alignment pattern line comprises a trench or dam formed in the first semiconductor chip.

4 . The semiconductor package of claim 2 , wherein the alignment pattern line comprises one of:
a first trench having a line shape and formed in a protective layer on the upper surface of the first semiconductor chip, a first line of a second trench having a quadrangular ring shape and formed in the protective layer, wherein the first line of the second trench is adjacent to the first edge of the upper surface of the first semiconductor chip, a first dam having a line shape and formed on the upper surface of the first semiconductor chip, and a first line of a second dam having a quadrangular ring shape and formed on the upper surface of the first semiconductor chip, wherein the first line of the second dam is adjacent to the first edge of the upper surface of the first semiconductor chip.

5 . The semiconductor package of claim 4 , wherein:
the alignment pattern line is formed by the first line of the second trench, and three lines, other than the first line of the second trench, are spaced a certain distance from three edges, other than the first edge of the upper surface of the first semiconductor chip, or from expose regions of the upper surface of the first semiconductor chip adjacent to the three edges of the first semiconductor chip.

6 . The semiconductor package of claim 4 ,
wherein the alignment pattern line is formed by the first line of the second dam, and wherein a gap exists between the first semiconductor chip and the second semiconductor chip and is adjacent to three lines other than the first line of the second dam.

7 . The semiconductor package of claim 1 , wherein a semiconductor chip that is lowermost among the at least two semiconductor chips is bonded to the package substrate without an adhesive.

8 . The semiconductor package of claim 7 ,
wherein the lowermost semiconductor chip is disposed on a solder resist (SR) open region of the package substrate, and wherein the SR open region is formed by removing a portion of an SR layer on an upper surface of the package substrate.

9 . The semiconductor package of claim 1 , wherein the semiconductor package has one of:
a thickness less than that of a first semiconductor package comprising an adhesive by a thickness of the adhesive, and a thickness that is substantially the same thickness as the first semiconductor package, with each of the at least two semiconductor chips being thicker than a semiconductor chip of the first semiconductor package.

10 . The semiconductor package of claim 1 , wherein a semiconductor chip that is lowermost among the at least two semiconductor chips is bonded to the package substrate with an adhesive.

11 . The semiconductor package of claim 1 , wherein the at least two semiconductor chips are stacked in a step shape or zigzag shape on the package substrate.

12 . A semiconductor package comprising:
a package substrate having a solder resist (SR) layer formed on an upper surface thereof; a first semiconductor chip coupled to the package substrate without an adhesive, the first semiconductor chip being electrically connected to the package substrate via a first wire; and at least two second semiconductor chips coupled to the first semiconductor chip without an adhesive, the at least two second semiconductor chips being electrically connected to the package substrate via a second wire, wherein a lower second semiconductor chip, among the at least two second semiconductor chips, located on a lower side is coupled, without an adhesive, to an upper second semiconductor chip located above the lower second semiconductor chip, wherein the lower second semiconductor chip that is lowermost among the at least two second semiconductor chips is self-aligned with a first alignment pattern line on an upper surface of the first semiconductor chip, and wherein the upper second semiconductor chip is self-aligned with a second alignment pattern line on an upper surface of the lower second semiconductor chip.

13 . The semiconductor package of claim 12 ,
wherein each of the first semiconductor chip and the at least two second semiconductor chips has an upper surface and a lower surface having rectangular shapes, and the upper surface comprises an active surface and the lower surface comprises a non-active surface, wherein the first alignment pattern line and the second alignment pattern line are adjacent to first edges that correspond to one line of the rectangular shapes of the upper and lower surfaces of the first semiconductor chip and the at least two second semiconductor chips and extend in the first direction, and the first alignment pattern line and the second alignment pattern line extend parallel to the first edges on the upper surfaces of the first semiconductor chip and the at least two second semiconductor chips, wherein the first edge of the lower second semiconductor chip that is the lowermost among the at least two second semiconductor chips is self-aligned with the first alignment pattern line of the first semiconductor chip, and wherein the first edge of the upper second semiconductor chip is self-aligned with the second alignment pattern line of the lower second semiconductor chip.

14 . The semiconductor package of claim 13 , wherein the first alignment pattern line or the second alignment pattern line comprises one of:
a first trench having a line shape and formed in a protective layer on the upper surface of the first semiconductor chip or the lower second semiconductor chip, a first line of a second trench having a quadrangular ring shape and formed in the protective layer, wherein the first line of the second trench is adjacent to the first edge of the upper surface of the first semiconductor chip or the lower second semiconductor chip, a first dam having a line shape and formed on the upper surface of the first semiconductor chip or the lower second semiconductor chip, and a first line of a second dam having a quadrangular ring shape and formed on the upper surface of the first semiconductor chip or the lower second semiconductor chip, wherein the first line of the second dam is adjacent to the first edge of the upper surface of the first semi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kwangyong

Classifications

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/865

  Die-attach connectors and bond wires · CPC title

• H10W46/301 Primary

  for alignment · CPC title

• H10W90/00

  Package configurations · CPC title