Package architecture with bridge dies having air gaps around vias

Patent metadata

Field	Value
Publication number	US-2025062206-A1
Application number	US-202318451150-A
Country	US
Kind code	A1
Filing date	Aug 17, 2023
Priority date	Aug 17, 2023
Publication date	Feb 20, 2025
Grant date	—

Abstract

Embodiments of a semiconductor die comprise: a first bond-pad on a first surface to couple to a package substrate, a second bond-pad on a second surface, the second surface being opposite to the first surface, a hole through the semiconductor die, a conductive pillar within the hole separated from sidewalls of the hole by an air gap, the conductive pillar coupled to the first bond-pad and the second bond-pad, and pathways conductively coupling at least two integrated circuit (IC) dies proximate to the second surface.

First claim

1 . A semiconductor die, comprising:
a first bond-pad on a first surface to couple to a package substrate; a second bond-pad on a second surface, the second surface being opposite to the first surface; a hole through the semiconductor die; a conductive pillar within the hole separated from sidewalls of the hole by an air gap, the conductive pillar coupled to the first bond-pad and the second bond-pad; and pathways conductively coupling at least two integrated circuit (IC) dies proximate to the second surface.

2 . The semiconductor die of claim 1 , wherein the first bond-pad and the second bond-pad are wider than the hole.

3 . The semiconductor die of claim 1 , wherein the first bond-pad is directly coupled to an interconnect of one of the IC dies.

4 . The semiconductor die of claim 1 , wherein the second bond-pad is directly coupled to an interconnect of the package substrate.

5 . The semiconductor die of claim 1 , wherein the semiconductor die is within a cavity in the package substrate.

6 . The semiconductor die of claim 1 , wherein:
the conductive pillar has a first width proximate to the first bond-pad and a second width proximate to the second bond-pad, and the first width is larger than the second width.

7 . The semiconductor die of claim 1 , wherein:
the conductive pillar is in a first portion of the semiconductor die, the pathways are in a second portion of the semiconductor die, and the first portion and the second portion are mutually exclusive.

8 . The semiconductor die of claim 7 , wherein:
the first portion is proximate to a periphery of the semiconductor die, and the second portion is proximate to a center of the semiconductor die.

9 . The semiconductor die of claim 1 , wherein:
the semiconductor die is coupled to the IC dies by a first interconnect and a second interconnect, the first interconnect is physically coupled to the conductive pillar, and the second interconnect is physically coupled to the pathways.

10 . The semiconductor die of claim 1 , wherein the pathways comprise conductive traces and conductive vias in interlayer dielectric (ILD) material.

11 . An integrated circuit (IC) package, comprising:
a package substrate having a surface with a blind cavity extending partially through the package substrate from the surface; a plurality of IC dies attached to the surface of the package substrate; and a bridge die in the blind cavity attached to the plurality of IC dies, the bridge die comprising:
conductive pathways conductively coupling at least a pair of IC dies in the plurality if IC dies;
through-silicon vias (TSVs) extending through a thickness of the bridge die; and
an air gap around at least one TSV.

12 . The IC package of claim 11 , wherein:
the TSV is in a hole, the hole has substantially parallel sidewalls perpendicular to the surface, and the air gap is between the TSV and the sidewalls.

13 . The IC package of claim 11 , wherein:
the plurality of IC dies is directly coupled to the bridge die by at least first interconnects and second interconnects, and the first interconnects are larger than the second interconnects.

14 . The IC package of claim 13 , wherein the second interconnects are similar in size to the first interconnects.

15 . The IC package of claim 13 , wherein:
the bridge die is directly coupled to the package substrate by third interconnects, and the third interconnects are similar in size to the first interconnects.

16 . A package substrate, comprising:
buildup layers; a cavity in the buildup layers; and a semiconductor die in the cavity, the semiconductor die comprising a plurality of conductive vias proximate to a periphery of the semiconductor die, wherein:
each conductive via extends through a thickness of the semiconductor die, and
an air gap surrounds each conductive via.

17 . The package substrate of claim 16 , wherein:
each air gap is capped by a bond-pad on either end of the air gap, and the corresponding conductive via within the air gap is directly coupled to the bond-pads on either end of the air gap.

18 . The package substrate of claim 17 , wherein the bond-pads are wider than the air gap.

19 . The package substrate of claim 16 , wherein:
the semiconductor die comprises: a substrate including silicon; layers of metallization including conductive traces; interlayer dielectric (ILD) material between the layers and in the layers between the conductive traces; and conductive vias through the ILD material, and the air gap around each conductive via extends through the substrate and the ILD material.

20 . The package substrate of claim 16 , wherein:
the semiconductor die is coupled to interconnects at a bottom of the cavity, and each interconnect is directly coupled to one of the conductive vias.

Assignees

• Intel Corp

Inventors

• Marin Brandon C
• Duan Gang
• Pietambaram Srinivas V
• Ecton Jeremy

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/635 Primary

  Through-vias · CPC title