DIE BACKSIDE PROFILE for SEMICONDUCTOR DEVICES

Patent metadata

Field	Value
Publication number	US-2025062129-A1
Application number	US-202318450466-A
Country	US
Kind code	A1
Filing date	Aug 16, 2023
Priority date	Aug 16, 2023
Publication date	Feb 20, 2025
Grant date	—

Abstract

Embodiments of the disclosure include an apparatus and method of forming a backside profile in a semiconductor device that includes die-to-wafer bonding. The method generally includes removing a portion of a substrate layer included in a plurality of dies, the plurality of dies arranged on and bonded to an insulation layer included in a support structure, where the plurality of dies define a plurality of channels between adjacent dies, and forming a corner feature on a plurality of corners of the substrate layer adjacent to the plurality of channels. The use of a backside profile as described herein may mitigate the downstream process risks associated with trapped residue in the channels, and provide stress relief to the semiconductor device.

First claim

We claim:

1 . A method, comprising:
removing a portion of a substrate layer included in a plurality of dies, the plurality of dies arranged on and bonded to an insulation layer included in a support structure, wherein the plurality of dies define a plurality of channels between adjacent dies; and forming a corner feature on a plurality of corners of the substrate layer adjacent to the plurality of channels.

2 . The method of claim 1 , wherein at least one sidewall of at least one of the plurality of dies is tapered, and wherein an angle of the at least one tapered sidewall is between 60 degrees and 85 degrees.

3 . The method of claim 1 , wherein a radius of the corner feature is between 5 micrometers (μm) and 20 μm.

4 . The method of claim 1 , wherein an angle of the corner feature is between 5 degrees and 45 degrees.

5 . The method of claim 1 , wherein a distance between a sidewall of the plurality of dies and a global interconnect included in the plurality of dies and the support structure is at least 10 micrometers (μm), and wherein the corner feature is disposed between the sidewall and the global interconnect.

6 . The method of claim 1 , wherein a length of the plurality of channels from a top of the corner feature on a first die of the plurality of dies to a top of the corner feature on a second die of the plurality of dies is between 50 micrometers (μm) and 4 millimeters (mm).

7 . The method of claim 1 , further comprising:
planarizing the substrate layer by a chemical mechanical planarization process.

8 . The method of claim 1 , wherein forming the corner feature on the plurality of corners comprises etching the corner feature by a first reactive ion etch (RIE) process.

9 . The method of claim 8 , wherein the first RIE process comprises using at least one of sulfur hexafluoride (SF 6 ), Oxygen (O 2 ), trifluoromethane (CHF 3 ), octafluorocyclobutane (C 4 F 8 ), or methyl fluoride (CH 3 F).

10 . The method of claim 9 , wherein the first RIE process comprises using a radio frequency between 400 kilohertz (KHz) and 14 megahertz (MHz), radio frequency power less than 7 kilowatts (kW), a flow rate less than 2000 standard cubic centimeters per minute (sccm), and a pressure between 20 milla Torr (mT) and 250 mT, for a duration less than 5 minutes.

11 . The method of claim 10 , wherein removing the portion of the substrate layer included in the plurality of dies comprises etching the portion of the substrate layer by a second RIE process.

12 . The method of claim 11 , wherein a ratio of a selectivity of the second RIE process between the substrate layer and the insulation layer is at least 100:1.

13 . The method of claim 12 , wherein the second RIE process comprises using at least one of SF 6 , CH 3 F, or C 4 F 8 .

14 . The method of claim 13 , wherein the second RIE process comprises using a radio frequency between 400 kilohertz (KHz) and 14 megahertz (MHz), radio frequency power less than 7 kilowatts (kW), a flow rate less than 2000 standard cubic centimeters per minute (sccm), and a pressure between 20 milla Torr (mT) and 80 mT, for a duration less than 10 minutes.

15 . An interconnect structure, comprising:
a support structure including an insulation layer; a plurality of dies arranged on and bonded to the insulation layer, wherein the plurality of dies include a substrate layer, and wherein the plurality of dies define a plurality of channels between adjacent dies; and a corner feature included on a plurality of corners of the substrate layer adjacent to the plurality of channels.

16 . The interconnect structure of claim 15 , wherein at least one sidewall of at least one of the plurality of dies is tapered, and wherein an angle of the at least one tapered sidewall is between 60 degrees and 85 degrees.

17 . The interconnect structure of claim 15 , wherein a radius of the corner feature is between 5 micrometers (μm) and 20 μm.

18 . The interconnect structure of claim 15 , wherein an angle of the corner feature is between 5 degrees and 45 degrees.

19 . An interconnect structure, comprising:
a support structure including an insulation layer; and a plurality of dies arranged on and bonded to the insulation layer, wherein the plurality of dies include a substrate layer, wherein the plurality of dies define a plurality of channels between adjacent dies, and wherein at least one sidewall of at least one of the plurality of dies is tapered.

20 . The interconnect structure of claim 15 , further comprising:
a corner feature included on a plurality of corners of the substrate layer adjacent to the plurality of channels.

Assignees

• Applied Materials Inc

Inventors

• Lim Yin Wei
• See Guan Huei
• Yong Chang Bum
• Lianto Prayudi
• Sundarrajan Arvind
• Sun Cheng

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title