High-frequency drain-extended metal-oxide-semiconductor (demos) devices and methods for producing the same

Patent metadata

Field	Value
Publication number	US-2025056829-A1
Application number	US-202418926281-A
Country	US
Kind code	A1
Filing date	Oct 24, 2024
Priority date	Nov 21, 2023
Publication date	Feb 13, 2025
Grant date	—

Abstract

Provided are a DEMOS device and a method for producing the same. The DEMOS device includes a silicon substrate, a well region, a source region, a drain region, a drift region, a lightly doped region, a gate structure, and a field plate structure. The gate structure includes a primary gate structure and a secondary gate structure. The primary gate structure is disposed on a p-type well or an n-type well of the well region, and configured to receive an input signal. The secondary gate structure covers part of the p-type well and part of the drift region, or part of the n-type well and part of the drift region. The secondary gate structure is configured to receive a fixed bias voltage. The short gate length of the primary gate structure significantly reduces gate-drain capacitance, and increases cutoff frequency, enhancing high-frequency performance, while having minimal impact on breakdown voltage.

First claim

What is claimed is:

1 . A high-frequency drain-extended metal-oxide-semiconductor (DEMOS) device, comprising a silicon substrate, a well region, a source region, a drain region, a drift region, a lightly doped region, a gate structure, and a field plate structure, wherein
the gate structure includes a primary gate structure and a secondary gate structure, the primary gate structure is disposed on a p-type well or an n-type well of the well region, and the primary gate structure is configured to receive an input signal; the secondary gate structure covers part of the p-type well and part of the drift region, or the secondary gate structure covers part of the n-type well and part of the drift region; the secondary gate structure is configured to receive a fixed bias voltage; a gate length of the primary gate structure is smaller than a gate length of a gate structure of a conventional DEMOS device; the lightly doped region is disposed on a surface of the p-type well or a surface of the n-type well, and the lightly doped region is located between the primary gate structure and the secondary gate structure; and the field plate structure covers the lightly doped region.

2 . The high-frequency DEMOS device of claim 1 , wherein the gate length of the primary gate structure satisfies a predetermined gate length condition, the predetermined gate length condition being related to a minimum allowable gate length of the primary gate structure under a current process node.

3 . The high-frequency DEMOS device of claim 1 , wherein a material of the field plate structure is a high dielectric constant material.

4 . The high-frequency DEMOS device of claim 1 , wherein the primary gate structure includes a gate oxide layer, a gate polysilicon layer, and a silicon nitride sidewall.

5 . The high-frequency DEMOS device of claim 1 , wherein the secondary gate structure includes a gate oxide layer, a gate polysilicon layer, and a silicon nitride sidewall.

6 . A method of producing a high-frequency DEMOS device, the high-frequency DEMOS device being the high-frequency DEMOS device of claim 1 , and the method comprising:
providing a p-type epitaxial substrate having an n-type buried layer, and performing localized oxidation isolation on a portion of the p-type epitaxial substrate to define an active region of the high-frequency DEMOS device; implanting and diffusing n-type ions and p-type ions separately into a DEMOS region to form the n-type well, the drift region, and the p-type well of the high-frequency DEMOS device; growing a gate oxide layer and depositing polycrystalline silicon in the DEMOS region to form the primary gate structure and the secondary gate structure of the high-frequency DEMOS device; lightly implanting ions into the region between the primary gate structure and the secondary gate structure to form the lightly doped region of the high-frequency DEMOS device; depositing a layer of a high dielectric constant material on the lightly doped region to form the field plate structure of the high-frequency DEMOS device; forming a silicon nitride sidewall isolation structure of the primary gate structure and a silicon nitride sidewall isolation structure of the secondary gate structure in the DEMOS region; and performing self-alignment and separately implanting a predetermined dose of n-type ions and p-type ions in an isolation ring lead-out region, the source region, the drain region, a substrate electrode lead-out region, and a body electrode lead-out region of the DEMOS region to form an n-type isolation ring lead-out region, an n-type source region, an n-type drain region, a p-type substrate electrode lead-out region, and a p-type body electrode lead-out region of the high-frequency DEMOS device; or performing self-alignment and separately implanting the predetermined dose of n-type ions and p-type ions in the isolation ring lead-out region, the source region, the drain region, the substrate electrode lead-out region, and the body electrode lead-out region of the DEMOS region to form the n-type isolation ring lead-out region, an n-type body electrode lead-out region, the p-type substrate electrode lead-out region, a p-type source region, and a p-type drain region of the high-frequency DEMOS device; the predetermined dose being not less than a preset value.

7 . The method of claim 6 , further comprising:
controlling an initial implantation dose of an ion implantation device, and modulating an initial junction depth of the lightly doped region, wherein the initial implantation dose is determined based on a historical breakdown voltage.

8 . The method of claim 7 , further comprising:
collecting, by a test device, an actual junction depth of the lightly doped region and an actual deposition thickness of the high dielectric constant material; determining a predicted breakdown voltage of the high-frequency DEMOS device based on the actual junction depth and the actual deposition thickness; and adjusting the initial implantation dose of the ion implantation device based on the predicted breakdown voltage.

9 . The method of claim 6 , further comprising:
depositing, by a thin film deposition device, the high dielectric constant material on the lightly doped region to obtain the high dielectric constant material with an initial deposition thickness, control of the initial deposition thickness being achieved by controlling an initial deposition time of the thin film deposition device.

10 . The method of claim 9 , further comprising:
collecting, by a test device, an actual junction depth of the lightly doped region and an actual deposition thickness of the high dielectric constant material; determining a predicted breakdown voltage of the high-frequency DEMOS device based on the actual junction depth and the actual deposition thickness; and adjusting the initial deposition time of the thin film deposition device based on the predicted breakdown voltage.

11 . The method of claim 10 , wherein the determining a predicted breakdown voltage of the high-frequency DEMOS device based on the actual junction depth and the actual deposition thickness includes:
determining a predicted breakdown voltage range of the high-frequency DEMOS device via a breakdown model based on the actual junction depth, the actual deposition thickness, a type of the lightly doped region, and a type of the high dielectric constant material, wherein the breakdown model is a machine learning model, the breakdown model is obtained by training an initial breakdown model with a training dataset, the training dataset includes a plurality of sub-training datasets, a sub-training dataset of the plurality of sub-training datasets includes a plurality of training samples and labels corresponding to the plurality of training samples, respectively; and a training process of the breakdown model includes: obtaining the plurality of sub-training datasets based on different historical breakdown voltages corresponding to a same type of historical high-frequency DEMOS devices in historical processing data, wherein the labels corresponding to the plurality of training samples of the sub-training dataset are the same; and adjusting a learning rate of the initial breakdown model corresponding to the training dataset based on a stability degree of output results of each of the plurality of sub-training datasets.

12 . The method of claim 10 , wherein the determining a predicted breakdown voltage of the high-frequency DEMOS device based on the actual junction depth and the actual deposition thickness includes:
determining a target junction depth based on a plurality of actual junction depths; determining a

Assignees

• Univ Zhejiang
• Beijing Smartchip Microelectronics Tech Co Ltd

Inventors

• Xu Kai
• Wu Bo
• Huang Xiaoyun
• Chen Yanning
• Liu Fang
• Gao Dawei
• Wu Yongyu

Classifications

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/204 Primary

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title