Info packages including thermal dissipation blocks

Patent metadata

Field	Value
Publication number	US-2025054775-A1
Application number	US-202418933764-A
Country	US
Kind code	A1
Filing date	Oct 31, 2024
Priority date	May 13, 2021
Publication date	Feb 13, 2025
Grant date	—

Abstract

A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.

First claim

What is claimed is:

1 . A method comprising:
forming a package comprising:
forming a plurality of redistribution lines over a carrier;
forming a thermal dissipation block over the carrier, wherein the forming the thermal dissipation block comprises:
forming a first redistribution line with a portion in a first dielectric layer; and
forming a second redistribution line with a portion in a second dielectric layer, wherein the second redistribution line is over and electrically connected to the first redistribution line;

placing a device die over the carrier; and
encapsulating the device die in a molding compound; and
de-bonding the package from the carrier, wherein in the package that is de-bonded from the carrier, the thermal dissipation block is either electrically floating or electrically grounded.

2 . The method of claim 1 , wherein the device die comprises a top surface dielectric layer, and wherein the first redistribution line comprises a via, and wherein a bottom surface of the via physically contacts a top surface of the top surface dielectric layer.

3 . The method of claim 2 , wherein the forming the first redistribution line comprises:
forming the first dielectric layer over and contacting the device die; and patterning the first dielectric layer to form an opening, wherein the top surface of the top surface dielectric layer is exposed to the opening, and wherein the via is formed in the opening.

4 . The method of claim 2 , wherein an entirety of the bottom surface of the via contacts the top surface of the top surface dielectric layer.

5 . The method of claim 1 further comprising:
forming a third redistribution line partially in the first dielectric layer; and
forming a fourth redistribution line over the third redistribution line, wherein the fourth redistribution line electrically connects the first redistribution line to the third redistribution line.

6 . The method of claim 5 further comprising:
forming a fifth redistribution line in the first dielectric layer, wherein the fifth redistribution line is physically located between the first redistribution line and the third redistribution line, and the fifth redistribution line is electrically coupled to the device die.

7 . The method of claim 6 further comprising forming an electrical connector over and electrically coupling to the thermal dissipation block, wherein the electrical connector and the thermal dissipation block are electrically floating.

8 . The method of claim 1 , wherein the thermal dissipation block is formed before the device die is placed, and the thermal dissipation block is on a backside of the device die.

9 . The method of claim 1 , wherein the thermal dissipation block is formed after the device die is placed, and the thermal dissipation block is on a front side of the device die.

10 . The method of claim 9 further comprising, before the device die is placed, forming an additional thermal dissipation block, wherein the additional thermal dissipation block is electrically floating.

11 . The method of claim 10 , wherein the thermal dissipation block overlaps the device die, and the additional thermal dissipation block is overlapped by the device die.

12 . A method comprising:
placing a device die over a carrier, wherein the device die comprises a top surface dielectric layer; forming a plurality of dielectric layers over the device die; and forming a first thermal dissipation block in the plurality of dielectric layers, wherein the forming the first thermal dissipation block comprises a plurality of plating processes to plate metal features in the plurality of dielectric layers, and wherein the forming the first thermal dissipation block comprises:
forming a first conductive feature in lower dielectric layers of the plurality of dielectric layers, wherein the first conductive feature comprises a via contacting the top surface dielectric layer; and
forming a second conductive feature in upper dielectric layers of the plurality of dielectric layers, wherein the first conductive feature and the second conductive feature are electrically interconnected.

13 . The method of claim 12 , wherein an entirety of a bottom surface of the via contacts the top surface dielectric layer.

14 . The method of claim 12 , wherein the first thermal dissipation block is electrically floating.

15 . The method of claim 12 , wherein an entirety of the first thermal dissipation block is enclosed in dielectric materials.

16 . The method of claim 12 further comprising forming a second thermal dissipation block over the carrier, wherein the device die is placed over the second thermal dissipation block.

17 . The method of claim 12 further comprising de-bonding the first thermal dissipation block from the carrier.

18 . The method of claim 12 further comprising forming an under-bump metallurgy electrically connecting to the first thermal dissipation block, wherein the first thermal dissipation block and the under-bump metallurgy are collectively electrically floating.

19 . A method comprising:
forming a plurality of dielectric layers over a carrier; placing a device die over the carrier, wherein the device die comprises a top surface dielectric layer; forming a thermal dissipation block over the device die, wherein the thermal dissipation block comprises first portions in the plurality of dielectric layers, and wherein all surfaces of the thermal dissipation block are in physical contact with dielectric materials of the plurality of dielectric layers; forming an electrical path comprising second portions in the plurality of dielectric layers; forming an electrical connector over and electrically coupling to the electrical path; and de-bonding a package component comprising the device die and the thermal dissipation block from the carrier.

20 . The method of claim 19 , wherein the first portions and the second portions are formed sharing common processes.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Ching-Yi
• Chen Yu-Hao
• Chang Fong-Yuan
• Huang Po-Hsiang
• Lee Jyh Chwen Frank
• Chen Shuo-Mao

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title