Vector floating-point classification

Patent metadata

Field	Value
Publication number	US-2025053420-A1
Application number	US-202418928702-A
Country	US
Kind code	A1
Filing date	Oct 28, 2024
Priority date	May 24, 2019
Publication date	Feb 13, 2025
Grant date	—

Abstract

Systems and methods enable the classification of each value of multiple floating-point values stored in a first vector register, and storage in a second vector register multiple elements that each indicate a respective classification of a respective value of the multiple floating-point values. A system includes a functional unit, first and second vector registers coupled to the functional unit, and processing circuitry. The processing circuitry is configurable, e.g., via an instruction, to cause the functional unit to perform the classification and storage operations.

First claim

What is claimed is:

1 . A system comprising:
a functional unit; a first vector register coupled to the functional unit; a second vector register coupled to the functional unit; and processing circuitry configurable to cause the functional unit to:
classify each value of multiple floating-point values stored in the first vector register, and
store in a second vector register multiple elements that each indicate a respective classification of a respective value of the multiple floating-point values.

2 . The system of claim 1 , wherein the processing circuitry is further configurable to store a first vector that includes the multiple floating-point values in the first vector register.

3 . The system of claim 1 , wherein the processing circuitry is further configurable to cause the functional unit, in performing the store operation, to store a second vector in the second vector register, in which the second vector includes the multiple elements.

4 . The system of claim 1 , wherein the functional unit is configured to classify each value of the multiple floating-point values by determining whether the respective value represents a zero value, a subnormal value, a normal value, an infinite value, a not a number (NaN) value, a quiet NaN (QNaN) value, or a signaling NaN (SNaN) value.

5 . The system of claim 4 , wherein the multiple floating-point values are included in a first vector and the multiple elements are included in a second vector, wherein the functional unit is configured to indicate:
a zero value in the first vector by a value of 0 in the second vector; a subnormal value in the first vector by a value of 1 in the second vector; a normal value in the first vector by a value of 2 in the second vector; an infinite value in the first vector by a value of 3 in the second vector; an NaN value in the first vector by a value of 4 in the second vector; and a SNaN value in the first vector by a value of 8 in the second vector.

6 . The system of claim 1 , further comprising a set of functional units, each configured to classify the multiple floating-point values, wherein the processing circuitry is further configurable to specify the functional unit from among the set of functional units.

7 . The system of claim 1 , further comprising:
a scalar datapath; and a vector datapath that includes the functional unit, wherein the processing circuitry is further configurable to specify the vector datapath.

8 . The system of claim 1 , wherein the processing circuitry is further configurable to specify whether the multiple floating-point values are single precision or double precision.

9 . The system of claim 1 , wherein:
each value of the multiple floating-point values includes a respective exponent; and the functional unit is configured to determine whether a respective value of the multiple floating-point values represents either an infinite value or a not-a-number value based on the respective exponent.

10 . The system of claim 9 , wherein:
each value of the multiple floating-point values includes a respective fraction; and the functional unit is configured to distinguish whether a respective value of the multiple floating-point values represents the infinite value or the not-a-number value based on the respective fraction.

11 . The system of claim 1 , wherein:
a size of the first vector register is different from a size of the second vector register.

12 . A method comprising:
storing a first vector that includes a set of floating-point values in a first vector register; and classifying, by a functional unit operably coupled to the first vector register, each value of the set of floating-point values stored in the first vector register; and storing, by the functional unit, in a second vector register, a second vector that includes a set of elements, each indicating a respective classification of a respective value of the set of floating-point values of the first vector.

13 . The method of claim 12 , wherein the classifying includes determining whether each value of the set of floating-point values represents a zero value, a subnormal value, a normal value, an infinite value, a not a number (NaN) value, a quiet NaN (QNaN) value, or a signaling NaN (SNaN) value.

14 . The method of claim 12 , further comprising receiving an instruction that specifies the functional unit from among a set of functional units.

15 . The method of claim 12 , further comprising receiving an instruction that specifies whether the set of floating-point values are single precision or double precision.

16 . The method of claim 12 , wherein:
each value of the set of floating-point values includes a respective exponent; and the classifying includes determining whether a respective value of the set of floating-point values represents either an infinite value or a not-a-number value based on the respective exponent.

17 . The method of claim 16 , wherein:
each value of the set of floating-point values includes a respective fraction; and the classifying includes distinguishing whether a respective value of the set of floating-point values represents the infinite value or the not-a-number value based on the respective fraction.

18 . The method of claim 12 , wherein a size of the first vector is different from a size of the second vector.

19 . The method of claim 18 , wherein the first vector has a size of 512 bits and the second vector has a size of 64 bits.

Assignees

• Texas Instruments Inc

Inventors

• Zbiciak Joseph
• Huber Brett L
• Bui Duc

Classifications

• G06F9/30038

  using a mask · CPC title

• G06F18/24

  Classification techniques · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06F9/30014

  with variable precision · CPC title