Array substrate, display device and driving circuit

Patent metadata

Field	Value
Publication number	US-2025035996-A1
Application number	US-202418915374-A
Country	US
Kind code	A1
Filing date	Oct 15, 2024
Priority date	Jul 29, 2022
Publication date	Jan 30, 2025
Grant date	—

Abstract

An array substrate, a display device, and a driving circuit are disclosed. The array substrate includes a substrate, a pixel electrode layer disposed on the substrate, a first insulating layer disposed on the substrate, multiple data lines disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the data lines, a common electrode layer disposed on the second insulating layer, and multiple data signal cancellation lines disposed between the common electrode layer and the first insulating layer. The common electrode layer includes multiple common shield electrode layers. The data signal cancellation lines are disposed in one-to-one correspondence with the data lines. Along the direction from the pixel electrode layer toward the common electrode layer, one common shield electrode layer covers one respective data signal cancellation line and one respective data line.

First claim

What is claimed is:

1 . An array substrate, comprising:
a substrate; a pixel electrode layer, disposed on the substrate; a first insulating layer, disposed on the substrate and covering the pixel electrode layer; a plurality of data lines, disposed on the first insulating layer; and a second insulating layer, disposed on the first insulating layer and covering the plurality of data lines; a common electrode layer, disposed on the second insulating layer, the common electrode layer comprising a plurality of common shield electrode layers; and a plurality of data signal cancellation lines, disposed between the common electrode layer and the first insulating layer, wherein the plurality of data signal cancellation lines are disposed in one-to-one correspondence with the plurality of data lines; wherein a voltage signal of each of the plurality of data signal cancellation lines has an opposite polarity to a voltage signal of the respective data line; wherein each of the plurality of data signal cancellation lines is disposed along an extending direction of the respective data line; wherein in a direction from the pixel electrode layer toward the common electrode layer, each of the plurality of common shield electrode layers covers one respective data signal cancellation line and one respective data line; wherein a gap is defined between a projection of each data line along a direction perpendicular to the substrate and a projection of the respective data signal cancellation line along the direction perpendicular to the substrate, and wherein a width of the gap is greater than or equal to a preset distance; wherein each of the plurality of data signal cancellation lines is disposed in the second insulating layer, and is disposed in a different layer from the respective data line, wherein a distance from the data signal cancellation line to the first insulating layer is greater than a distance from the data line layer to the first insulating layer; wherein in a direction from the pixel electrode layer toward the common electrode layer, the gap formed between a vertical projection of each of the plurality of data lines along a direction perpendicular to the substrate and a vertical projection of the respective data signal cancellation line along the direction perpendicular to the substrate is equal to the preset distance, the preset distance being greater than or equal to zero and being less than or equal to a difference between a width of the common electrode layer and a total width of the respective data signal cancellation line and respective data line.

2 . The array substrate of claim 1 , further comprising a gate metal layer, a source metal layer, a drain metal layer, and a semiconductor layer; wherein the gate metal layer is formed on the substrate; the first insulating layer covers the gate metal layer; the semiconductor layer is disposed on the first insulating layer; the source metal layer is disposed on the semiconductor layer; the drain metal layer is disposed on the semiconductor layer and opposite to the source metal layer; the drain metal layer is connected to the respective data line; the second insulating layer is disposed on the drain metal layer and the source metal layer; wherein the first insulating layer defines a via hole, and the pixel electrode layer is connected to the source metal layer through the via hole.

3 . The array substrate of claim 1 , wherein the voltage signal of each of the plurality of data signal cancellation lines has an opposite polarity to the voltage signal of the respective data line, and wherein the voltage signal of the data signal cancellation line has a different magnitude than that of the voltage signal of the respective data line.

4 . The array substrate of claim 1 , wherein along the extending direction of each of the plurality of data lines, a length of the respective data signal cancellation line is consistent with a length of the data line.

5 . The array substrate of claim 1 , wherein the width of each of the plurality of data signal cancellation lines is not equal to the width of the respective data line, and wherein the voltage signal of each of the plurality of data signal cancellation lines and the voltage signal of the respective data line have opposite polarities and unequal absolute values.

6 . An array substrate, comprising:
a substrate; a pixel electrode layer, disposed on the substrate; a first insulating layer, disposed on the substrate and covering the pixel electrode layer; a plurality of data lines, disposed on the first insulating layer; and a second insulating layer, disposed on the first insulating layer and covering the plurality of data lines; a common electrode layer, disposed on the second insulating layer, the common electrode layer comprising a plurality of common shield electrode layers; and a plurality of data signal cancellation lines, disposed between the common electrode layer and the first insulating layer, wherein the plurality of data signal cancellation lines are disposed in one-to-one correspondence with the plurality of data lines; wherein a voltage signal of each of the plurality of data signal cancellation lines has an opposite polarity to a voltage signal of the respective data line; wherein each of the plurality of data signal cancellation lines is disposed along an extending direction of the respective data line; wherein in a direction from the pixel electrode layer toward the common electrode layer, each of the plurality of common shield electrode layers covers one respective data signal cancellation line and one respective data line; wherein a gap is defined between a projection of each data line along a direction perpendicular to the substrate and a projection of the respective data signal cancellation line along the direction perpendicular to the substrate, and wherein a width of the gap is greater than or equal to a preset distance; wherein each of the plurality of data signal cancellation lines comprises a first data signal cancellation line and a second data signal cancellation line; wherein the first data signal cancellation line is disposed on a left side of the data line and is spaced apart from the respective data line, and the second data signal cancellation line is disposed on a right side of the data line and is spaced from the data line; wherein the voltage signal of the first data signal cancellation line and the voltage signal of the second data signal cancellation line have identical polarities; wherein both the voltage signal of the first data signal cancellation line and the voltage signal of the second data signal cancellation line have an opposite polarity to the voltage signal of the respective data line.

7 . The array substrate of claim 6 , further comprising a gate metal layer, a source metal layer, a drain metal layer, and a semiconductor layer; wherein the gate metal layer is formed on the substrate; the first insulating layer covers the gate metal layer; the semiconductor layer is disposed on the first insulating layer; the source metal layer is disposed on the semiconductor layer; the drain metal layer is disposed on the semiconductor layer and opposite to the source metal layer; the drain metal layer is connected to the respective data line; the second insulating layer is disposed on the drain metal layer and the source metal layer; wherein the first insulating layer defines a via hole, and the pixel electrode layer is connected to the source metal layer through the via hole.

8 . The array substrate of claim 6 , wherein the first data signal cancellation line and the second data signal cancellation line are arranged on the first insulating layer, and are arranged in the same layer as the respective data line.

Assignees

• Hkc Corp Ltd

Inventors

• Liu Yunyang
• Wang Jie
• Xu Yuchun
• Lv Li
• Zhang Guangchen
• Li Zhiwei
• Kang Baohong

Classifications

• G09G3/3614

  Control of polarity reversal in general · CPC title

• G02F1/136222

  Colour filters incorporated in the active matrix substrate · CPC title

• G02F1/136218

  Shield electrodes · CPC title

• G09G2320/0209

  Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title