3d-stacked semiconductor device manufactured using channel spacer

Patent metadata

Field	Value
Publication number	US-2025031444-A1
Application number	US-202318380476-A
Country	US
Kind code	A1
Filing date	Oct 16, 2023
Priority date	Jul 18, 2023
Publication date	Jan 23, 2025
Grant date	—

Abstract

Provided is a three-dimension (3D) stacked semiconductor device which includes: a 1stsource/drain region connected to a 1st channel structure; and a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure above the 1st channel structure, wherein the 2nd channel structure has a smaller length than the 1st channel structure in a channel-length direction, in which the 2nd source/drain region is connected to a 3rd source/drain region through the 2nd channel structure.

First claim

1 . A three-dimension (3D) stacked semiconductor device comprising:
a 1 st source/drain region connected to a 1 st channel structure; and a 2 nd source/drain region, above the 1 st source/drain region, connected to a 2 nd channel structure above the 1 st channel structure, wherein the 2 nd channel structure has a smaller length than the 1 st channel structure in a channel-length direction, in which the 2 nd source/drain region is connected to a 3 rd source/drain region through the 2 nd channel structure.

2 . The 3D-stacked semiconductor device of claim 2 , further comprising:
a gate structure surrounding the 1 st channel structure and the 2 nd channel structure; a 1 st inner spacer between a 1 st portion of the gate structure and the 1 st source/drain region; and a 2 nd inner spacer between a 2 nd portion of the gate structure and the 2 nd source/drain region, wherein the 2 nd inner spacer has a smaller length than the 1 st inner spacer in the channel-length direction.

3 . The 3D-stacked semiconductor device of claim 2 , wherein the 2 nd source/drain region has a greater length than the 1 st source/drain region in the channel-length direction.

4 . The 3D-stacked semiconductor device of claim 3 , wherein each of the 1 st channel structure and the 2 nd channel structure comprises a plurality of channel layers vertically stacked with a portion of a gate structure therebetween.

5 . The 3D-stacked semiconductor device of claim 1 , wherein the 2 nd source/drain region has a greater length than the 1 st source/drain region in the channel-length direction.

6 . The 3D-stacked semiconductor device of claim 5 , wherein the 2 nd source/drain region has a smaller width than the 1 st source/drain region in a channel-width direction, which intersects the channel-length direction.

7 . The 3D-stacked semiconductor device of claim 6 , wherein the 2 nd channel structure has a smaller width than the 1 st channel structure in the channel-width direction.

8 . The 3D-stacked semiconductor device of claim 7 , wherein each of the 1 st channel structure and the 2 nd channel structure comprises a plurality of channel layers vertically stacked with a portion of a gate structure therebetween.

9 . A three-dimension (3D) stacked semiconductor device comprising:
a 1 st source/drain region connected to a 1 st channel structure; and a 2 nd source/drain region, above the 1 st source/drain region, connected to a 2 nd channel structure above the 1 st channel structure, wherein the 2 nd source/drain region has a greater length than the 1 st source/drain region in a channel-length direction, in which the 2 nd source/drain region is connected to a 3 rd source/drain region through the 2 nd channel structure.

10 . The 3D-stacked semiconductor device of claim 9 , further comprising:
a gate structure surrounding the 1 st channel structure and the 2 nd channel structure; a 1 st inner spacer between a 1 st portion of the gate structure and the 1 st source/drain region; and a 2 nd inner spacer between a 2 nd portion of the gate structure and the 2 nd source/drain region, wherein the 2 nd inner spacer has a smaller length than the 1 st inner spacer in the channel-length direction.

11 . The 3D-stacked semiconductor device of claim 10 , wherein the 2 nd channel structure has a smaller length than the 1 st channel structure in the channel-length direction.

12 . The 3D-stacked semiconductor device of claim 11 , wherein each of the 1 st channel structure and the 2 nd channel structure comprises a plurality of channel layers vertically stacked with a portion of a gate structure therebetween.

13 . The 3D-stacked semiconductor device of claim 9 , wherein the 2 nd channel structure has a smaller length than the 1 st channel structure in the channel-length direction.

14 . The 3D-stacked semiconductor device of claim 9 , wherein the 2 nd source/drain region has a smaller width than the 1 st source/drain region in a channel-width direction, which intersects the channel-length direction.

15 . The 3D-stacked semiconductor device of claim 14 , wherein the 2 nd channel structure has a smaller length than the 1 st channel structure in a channel-length direction.

16 . The 3D-stacked semiconductor device of claim 15 , wherein the 2 nd channel structure has a smaller width than the 1 st channel structure in the channel-width direction.

17 . A three-dimension (3D) stacked semiconductor device comprising:
a 1 st source/drain region connected to a 1 st channel structure; a 2 nd source/drain region, above the 1 st source/drain region, connected to a 2 nd channel structure above the 1 st channel structure; a gate structure surrounding the 1 st channel structure and the 2 nd channel structure; a 1 st inner spacer between a 1 st portion of the gate structure and the 1 st source/drain region; and a 2 nd inner spacer between a 2 nd portion of the gate structure and the 2 nd source/drain region, wherein the 2 nd inner spacer has a smaller length than the 1 st inner spacer in a channel-length direction, in which the 2 nd source/drain region is connected to a 3 rd source/drain region through the 2 nd channel structure.

18 . The 3D-stacked semiconductor device of claim 17 , wherein the 2 nd channel structure has a smaller length than the 1 st channel structure in the channel-length direction

19 . The 3D-stacked semiconductor device of claim 17 , wherein the 2 nd source/drain region has a greater length than the 1 st source/drain region in the channel-length direction.

20 . The 3D-stacked semiconductor device of claim 17 , wherein the 2 nd source/drain region has a smaller width than the 1 st source/drain region in a channel-width direction, which intersects the channel-length direction.

21 - 23 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yun Seungchan
• Baek Jaejik
• Seo Kang-Ill

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/856 Primary

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title