Maintaining integrity of configuration data for memory systems

Patent metadata

Field	Value
Publication number	US-2025028598-A1
Application number	US-202418763967-A
Country	US
Kind code	A1
Filing date	Jul 3, 2024
Priority date	Jul 18, 2023
Publication date	Jan 23, 2025
Grant date	—

Abstract

Methods, systems, and devices for maintaining integrity of configuration data for memory devices are described. A memory system may implement an error control component configured to detect errors in configuration data stored to one or more mode registers. The error control component may be configured to generate error control information, including one or more parity bits or a checksum, associated with the configuration data. The memory system or a host system coupled with the memory system may be configured to detect errors in the configuration data based on the error control information. Based on detecting the errors, the memory system may enter a safe mode, in which the memory system refrains from performing access operations until the configuration data is rewritten to the one or more mode registers.

First claim

What is claimed is:

1 . An apparatus, comprising:
at least one memory device; and at least one controller coupled with the at least one memory device and configured to cause the apparatus to:
write information to one or more mode registers;
generate first error control information associated with the information based at least in part on writing the information to the one or more mode registers;
initiate a first operation to verify the information written to the one or more mode registers after generating the first error control information;
generate second error control information associated with the information written to the one or more mode registers based at least in part on initiating the first operation;
determine whether one or more errors are present in the information based at least in part on the first error control information and the second error control information; and
perform a second operation based at least in part on determining whether the one or more errors are present.

2 . The apparatus of claim 1 , wherein to determine whether the one or more errors are present, the at least one controller is further configured to cause the apparatus to:
determine that the one or more errors are present in the information based at least in part on comparing the first error control information with the second error control information.

3 . The apparatus of claim 2 , wherein to perform the second operation, the at least one controller is further configured to cause the apparatus to:
transmit an indication of the one or more errors to at least one host system, based at least in part on determining that the one or more errors are present.

4 . The apparatus of claim 2 , wherein to perform the second operation, the at least one controller is further configured to cause the apparatus to:
transmit the first error control information and the second error control information to at least one host system, wherein determining that the one or more errors are present is based at least in part on comparing, by the at least one host system, the first error control information with the second error control information.

5 . The apparatus of claim 1 , wherein the at least one controller is further configured to cause the apparatus to:
determine whether a periodic duration since a previous determination for whether the one or more errors are present has elapsed, wherein initiating the first operation is based at least in part on determining that the periodic duration has elapsed.

6 . The apparatus of claim 1 , wherein the at least one controller is further configured to cause the apparatus to:
receive a command to determine whether the one or more errors are present in the information, wherein initiating the first operation is based at least in part on receiving the command.

7 . The apparatus of claim 1 , wherein generating the second error control information is based at least in part on rewriting the information to the one or more mode registers.

8 . The apparatus of claim 1 , wherein the at least one controller is further configured to cause the apparatus to:
transmit the first error control information to at least one host system; and determine, by the at least one host system, that the one or more errors are present in the information based at least in part on transmitting the first error control information to the at least one host system.

9 . The apparatus of claim 1 , wherein the at least one controller is further configured to cause the apparatus to:
receive, from at least one host system, a mode register write command, wherein writing the information to the one or more mode registers is based at least in part on receiving the mode register write command.

10 . The apparatus of claim 9 , wherein the at least one controller is further configured to cause the apparatus to:
transition the at least one memory device from a lower power state to a higher power state, wherein receiving the mode register write command is based at least in part on transitioning the at least one memory device from the lower power state to the higher power state.

11 . The apparatus of claim 1 , wherein the at least one controller is further configured to cause the apparatus to:
enter a safe mode at the at least one memory device based at least in part on determining that the one or more errors are present in the information, wherein performing the second operation further comprises refraining from performing access operations on the at least one memory device based at least in part on entering the safe mode.

12 . The apparatus of claim 11 , wherein the at least one controller is further configured to cause the apparatus to:
rewrite the information to the one or more mode registers based at least in part on entering the safe mode; and exit the safe mode based at least in part on rewriting the information to the one or more mode registers.

13 . The apparatus of claim 1 , wherein:
the information comprises configuration data of a first size, the configuration data associated with operating the at least one memory device, and the first error control information and the second error control information are a second size different than the first size, the first error control information and the second error control information each comprising one or more parity bits associated with the information, or one or more checksums associated with the information.

14 . The apparatus of claim 1 , wherein the at least one controller is further configured to cause the apparatus to:
generate the first error control information at one or more error control components based at least in part on inputting the information from the one or more mode registers; store the first error control information to at least one flip flop coupled with the one or more error control components; and transmit an indication of the first error control information from the at least one flip flop to at least one host system.

15 . The apparatus of claim 14 , wherein the at least one controller is further configured to cause the apparatus to:
receive signaling at the at least one flip flop, the signaling comprising at least one clock signal indicating a frequency for transmitting the indication of the first error control information, wherein transmitting the indication to the at least one host system is based at least in part on the frequency.

16 . The apparatus of claim 1 , wherein the at least one controller is further configured to cause the apparatus to:
store the first error control information to at least one first flip flop coupled with one or more error control components based at least in part on first signaling, wherein the first error control information and the second error control information are generated by the one or more error control components; store the first error control information to at least one second flip flop coupled with the one or more error control components based at least in part on second signaling; compare, at one or more check components coupled with the at least one first flip flop and the at least one second flip flop, the first error control information and the second error control information based at least in part on the second signaling; and transmit a result of comparing the first error control information and the second error control information to at least one host system based at least in part on comparing the first error control information and the second error control information.

17 . The apparatus of claim 16 , whe

Assignees

• Micron Technology Inc

Inventors

• Richter Michael Dieter
• Hein Thomas
• Salobrena Garcia Casto

Classifications

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1056 Primary

  Updating check bits on partial write, i.e. read/modify/write · CPC title

• G06F11/141

  for bus or memory accesses · CPC title