Integrated circuit devices including stacked field-effect transistors in multi-height cells and methods of forming the same

Patent metadata

Field	Value
Publication number	US-2025022773-A1
Application number	US-202318492142-A
Country	US
Kind code	A1
Filing date	Oct 23, 2023
Priority date	Jul 13, 2023
Publication date	Jan 16, 2025
Grant date	—

Abstract

Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include an upper transistor including an upper channel region on a substrate, a lower transistor between the substrate and the upper transistor, the lower transistor including a lower channel region, and a power line extending longitudinally in a first horizontal direction. At least one of the upper channel region or the lower channel region may extend longitudinally in a second horizontal direction that traverses the first horizontal direction, and the at least one of the upper channel region or the lower channel region may overlap the power line in a thickness direction.

First claim

What is claimed is:

1 . An integrated circuit device comprising:
an upper transistor comprising an upper channel region on a substrate; a lower transistor between the substrate and the upper transistor, the lower transistor comprising a lower channel region; and a power line extending longitudinally in a first horizontal direction, wherein at least one of the upper channel region or the lower channel region extends longitudinally in a second horizontal direction that traverses the first horizontal direction, and the at least one of the upper channel region or the lower channel region overlaps the power line in a thickness direction.

2 . The integrated circuit device of claim 1 , wherein the at least one of the upper channel region or the lower channel region is electrically connected to a source/drain region that overlaps the power line in the thickness direction.

3 . The integrated circuit device of claim 1 , wherein the at least one of the upper channel region or the lower channel region comprises a central portion in the second horizontal direction that overlaps the power line in the thickness direction.

4 . The integrated circuit device of claim 1 , wherein the lower channel region overlaps the power line in the thickness direction, and the upper channel region is free of overlap with the power line in the thickness direction.

5 . The integrated circuit device of claim 4 , wherein a width of the lower channel region in the second horizontal direction is at least two times wider than a width of the upper channel region in the second horizontal direction.

6 . The integrated circuit device of claim 4 , wherein the upper transistor is a first upper transistor, and the upper channel region is a first upper channel region,
the integrated circuit device further comprises a second upper transistor comprising a second upper channel region that is spaced apart from the first upper channel region in the second horizontal direction, and the lower channel region overlaps the first and second upper channel regions in the thickness direction.

7 . The integrated circuit device of claim 1 , wherein the upper channel region overlaps the power line in the thickness direction, and the lower channel region is free of overlap with the power line in the thickness direction.

8 . The integrated circuit device of claim 7 , wherein a width of the upper channel region in the second horizontal direction is at least two times wider than a width of the lower channel region in the second horizontal direction.

9 . The integrated circuit device of claim 1 , wherein both the upper channel region and the lower channel region overlap the power line in the thickness direction.

10 . The integrated circuit device of claim 1 , wherein the power line is a first power line,
the integrated circuit device further comprises a second power line and a third power line that are spaced apart from each other in the second horizontal direction with the first power line therebetween, and the at least one of the upper channel region or the lower channel region comprises a portion that is spaced apart from the second and third power lines in the second horizontal direction by an equal distance.

11 . An integrated circuit device comprising:
a first transistor comprising a first channel region on a substrate; and a pair of second transistors, respectively, comprising a pair of second channel regions that are spaced apart from each other in a first horizontal direction, wherein the first channel region overlaps the pair of second channel regions in a thickness direction.

12 . The integrated circuit device of claim 11 , wherein the first channel region is between the substrate and the pair of second channel regions.

13 . The integrated circuit device of claim 11 , wherein the pair of second channel regions are between the substrate and the first channel region.

14 . The integrated circuit device of claim 11 , wherein the first channel region comprises:
a first portion that overlaps a first one of the pair of second channel regions in the thickness direction; a second portion that overlaps a second one of the pair of second channel regions in the thickness direction; and a third portion that is between the first and second portions and is free of overlap with the pair of second channel regions in the thickness direction.

15 . The integrated circuit device of claim 11 , further comprising a power line extending longitudinally in a second horizontal direction that traverses the first horizontal direction, wherein the first channel region overlaps the power line in the thickness direction.

16 . The integrated circuit device of claim 15 , wherein the pair of second channel regions are free of overlap with the power line in the thickness direction.

17 . The integrated circuit device of claim 11 , wherein a width of the first channel region in the first horizontal direction is wider than a combined width of the pair of second channel regions in the first horizontal direction.

18 . The integrated circuit device of claim 11 , wherein the first channel region is electrically connected to a first source/drain region,
the pair of second channel regions are electrically connected to second and third source/drain regions, respectively, and the first source/drain region overlaps the second and third source/drain regions in the thickness direction.

19 . A method of forming an integrated circuit device, the method comprising:
forming a lower transistor and an upper transistor on a substrate, the lower transistor comprising a lower channel region and the upper transistor comprising an upper channel region; and forming a power line extending longitudinally in a first horizontal direction, wherein at least one of the upper channel region or the lower channel region extends longitudinally in a second horizontal direction that traverses the first horizontal direction, and the at least one of the upper channel region or the lower channel region overlaps the power line in a thickness direction.

20 . The method of claim 19 , further comprising forming a source/drain region that is electrically connected to the at least one of the upper channel region or the lower channel region and overlaps the power line in the thickness direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jintae
• Yun Seungchan
• Seo Kang-Ill

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title