Techniques for data path address protection

Patent metadata

Field	Value
Publication number	US-2025013534-A1
Application number	US-202418762327-A
Country	US
Kind code	A1
Filing date	Jul 2, 2024
Priority date	Jul 7, 2023
Publication date	Jan 9, 2025
Grant date	—

Abstract

Methods, systems, and devices for techniques for data path address protection are described. As part of a write operation, the memory system may receive data associated with the write operation and an address for the data from a host system. The memory system may generate a first codeword using the address and may store both the first codeword and the data at the address. In some examples, the memory system may generate a second codeword using the data and the first codeword and store the second codeword along with the data and the first codeword. As part of a subsequent read operation for the data, the memory system may receive the address from the host system and retrieve the stored data and first codeword. The memory system may generate a third codeword using the address associated with the read operation and may compare the third codeword with the first codeword.

First claim

What is claimed is:

1 . A method, comprising:
receiving data associated with a write command and an address associated with the write command; generating a first codeword based at least in part on applying a function to the address; generating a second codeword based at least in part on applying an error control code to the first codeword and the data; and storing the second codeword at the address.

2 . The method of claim 1 , wherein generating the second codeword comprises:
appending the first codeword to the data to generate a combined codeword; and applying the error control code to the combined codeword, wherein the second codeword is based at least in part on an output of the error control code.

3 . The method of claim 1 , further comprising:
receiving, as part of an activate command, a row address associated with the data and a bank address associated with the data, wherein receiving the write command is based at least in part on receiving the activate command.

4 . The method of claim 3 , wherein receiving the write command comprises:
receiving a column address associated with the data, wherein generating the first codeword comprises applying the function to the bank address, the row address, and the column address.

5 . The method of claim 3 , further comprising:
storing, as part of executing the activate command, the row address at a bank associated with the bank address.

6 . The method of claim 1 , wherein the address comprises a bank address associated with the data, a row address associated with the data, and a column address associated with the data.

7 . The method of claim 1 , further comprising:
identifying, as part of a background operation and based at least in part on an address counter corresponding to the address, the first codeword based at least in part on retrieving the second codeword from the address; generating a third codeword based at least in part on applying the function to the address; and incrementing the address counter based at least in part on performing an error control procedure using the first codeword and the third codeword.

8 . The method of claim 7 , wherein performing the error control procedure comprises:
identifying an error in the first codeword; and storing an indication of the error, wherein incrementing the address counter is based at least in part on storing the indication.

9 . The method of claim 7 , wherein performing the error control procedure comprises:
determining that the first codeword and the third codeword match; and storing the first codeword at the address based at least in part on determining that the first codeword and the third codeword match.

10 . The method of claim 1 , wherein the function comprises an error control operation different than the error control code.

11 . A method, comprising:
receiving, from a host device, a read command for data and an address associated with the data; generating a first codeword based at least in part on applying a function to the address; identifying a second codeword stored in a memory array at the address; decoding the second codeword to obtain the data and a third codeword based at least in part on an error control code; performing an error control operation using the first codeword and the third codeword; and transmitting the data to the host device based at least in part on performing the error control operation.

12 . The method of claim 11 , further comprising:
identifying an address error based at least in part on comparing the first codeword and the third codeword; and transmitting an indication of the address error to the host device based at least in part on identifying address error.

13 . The method of claim 12 , further comprising:
storing an indication of the address error.

14 . The method of claim 13 , further comprising:
receiving a command to retrieve the indication of the address error, wherein transmitting the indication of the address error to the host device is further based at least in part on receiving the command to retrieve the indication of the address error.

15 . The method of claim 12 , further comprising:
receiving, based at least in part on identifying the address error, a command to disable one or more memory cells associated with the address; and disabling the one or more memory cells based at least in part on receiving the command to disable the one or more memory cells.

16 . The method of claim 11 , wherein identifying the second codeword comprises:
retrieving the second codeword from the address; and applying an error control code to the second codeword based at least in part on retrieving the second codeword.

17 . The method of claim 16 , wherein applying the error control code comprises:
identifying an error in the third codeword; and correcting the error, wherein performing the error control operation is based at least in part on correcting the error.

18 . The method of claim 11 , further comprising:
receiving, as part of an activate command, a row address associated with the data and a bank address associated with the data, wherein receiving the read command is based at least in part on receiving the activate command.

19 . The method of claim 11 , wherein performing the error control operation comprises:
determining whether the first codeword matches the third codeword.

20 . A method, comprising:
receiving data associated with a write command and an address associated with the write command; generating a first codeword based at least in part on applying a function to the address; generating a second codeword based at least in part on applying an error control code to the data; generating a third codeword based at least in part on applying a second function the first codeword and the second codeword; and storing the data and the third codeword in a memory array at the address.

21 . The method of claim 20 , wherein the second function comprises an Exclusive-OR operation.

22 . The method of claim 20 , wherein the first codeword and the second codeword each comprise a same quantity of bits.

23 . A method, comprising:
receiving, from a host device, a read command for data and an address associated with the data; generating a first codeword based at least in part on applying a function to the address; identifying a second codeword and a third codeword stored in a memory array at the address; generating an error control code based at least in part on applying a second function to the first codeword and the third codeword; decoding the second codeword to obtain the data based at least in part on the error control code; and transmitting the data to a host device based at least in part on decoding the second codeword.

24 . The method of claim 23 , further comprising:
identifying an address error based at least in part on applying the second function; and transmitting an indication of the address error to the host device based at least in part on identifying the address error.

25 . The method of claim 23 , wherein the second function comprises an Exclusive-OR operation.

Assignees

• Micron Technology Inc

Inventors

• Richter Michael Dieter
• Salobrena Garcia Casto
• Spirkl Wolfgang Anton
• Hein Thomas
• Mayer Peter

Classifications

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/1016 Primary

  Error in accessing a memory location, i.e. addressing error · CPC title