Bit and signal level mapping

Patent metadata

Field	Value
Publication number	US-2025013527-A1
Application number	US-202418888109-A
Country	US
Kind code	A1
Filing date	Sep 17, 2024
Priority date	Jan 22, 2020
Publication date	Jan 9, 2025
Grant date	—

Abstract

Methods, systems, and devices for bit and signal level mapping are described to enable a memory device to transmit or receive a multi-symbol signal that includes more than two (2) physical levels. Some cyclic redundancy check (CRC) calculations may generate one or more bits of CRC output per symbol of an associated signal and the output may be transmitted via a multi-symbol signal by converting one or more CRC output bit to a physical level of the signal. The conversion, or mapping, process may be performed such that the physical levels of the signal avoid a transition between a highest physical level and lowest physical level. For example, a modulation scheme or mapping process may be configured to map different values of CRC output bits to different physical levels, where the different physical levels are separated by one other physical level associated with the signal or the modulation scheme.

First claim

What is claimed is:

1 . A method by a memory system, comprising:
identifying respective quantities of first bits associated with respective portions of a signal modulated using a modulation scheme comprising four or more physical levels; determining a quantity of second bits based at least in part on performing a half-rate calculation using the respective quantities of first bits; and transmitting the signal based at least in part on mapping respective bits of the quantity of second bits with respective physical levels of the four or more physical levels.

2 . The method of claim 1 , further comprising:
performing the half-rate calculation at one or more processors based at least in part on combining respective quantities of first bits associated with respective portions of the signal to generate the quantity of second bits.

3 . The method of claim 1 , further comprising:
generating the respective quantities of first bits based at least in part on performing one or more cyclic redundancy check operations on the respective portions of the signal, wherein identifying the respective quantities of first bits is based at least in part on generating the respective quantities of first bits.

4 . The method of claim 1 , further comprising:
receiving the signal as a burst transmission, wherein identifying the respective quantities of first bits is based at least in part on receiving the signal.

5 . The method of claim 1 , further comprising:
converting a respective logic levels associated with the respective quantities of first bits to respective physical levels; and mapping the respective quantities of first bits to the respective physical levels based at least in part on converting the respective logic levels.

6 . The method of claim 1 , wherein each respective quantity of first bits and the quantity of second bits comprises a same quantity of bits.

7 . The method of claim 1 , wherein the first bits comprise cyclic redundancy check bits.

8 . The method of claim 1 , wherein each physical level is associated with a respective multi-bit symbol.

9 . The method of claim 1 , further comprising:
mapping one of the first bits with a termination level of the four or more physical levels, wherein each of the four or more physical levels is associated with one or more logic bits based at least in part on a gray coding scheme.

10 . A memory system, comprising:
one or more memory arrays; and processing circuitry coupled with the one or more memory arrays, and configured to cause the memory system to:
identify respective quantities of first bits associated with respective portions of a signal modulated using a modulation scheme comprising four or more physical levels;
determine a quantity of second bits based at least in part on performing a half-rate calculation using the respective quantities of first bits; and
transmit the signal based at least in part on mapping respective bits of the quantity of second bits with respective physical levels of the four or more physical levels.

11 . The memory system of claim 10 , wherein the processing circuitry is further configured to cause the memory system to:
perform the half-rate calculation at one or more processors based at least in part on combining respective quantities of first bits associated with respective portions of the signal to generate the quantity of second bits.

12 . The memory system of claim 10 , wherein the processing circuitry is further configured to cause the memory system to:
generate the respective quantities of first bits based at least in part on performing one or more cyclic redundancy check operations on the respective portions of the signal, wherein identifying the respective quantities of first bits is based at least in part on generating the respective quantities of first bits.

13 . The memory system of claim 10 , wherein the processing circuitry is further configured to cause the memory system to:
receive the signal as a burst transmission, wherein identifying the respective quantities of first bits is based at least in part on receiving the signal.

14 . The memory system of claim 10 , wherein the processing circuitry is further configured to cause the memory system to:
convert a respective logic levels associated with the respective quantities of first bits to respective physical levels; and map the respective quantities of first bits to the respective physical levels based at least in part on converting the respective logic levels.

15 . A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processing circuitry to:
identify respective quantities of first bits associated with respective portions of a signal modulated using a modulation scheme comprising four or more physical levels; determine a quantity of second bits based at least in part on performing a half-rate calculation using the respective quantities of first bits; and transmit the signal based at least in part on mapping respective bits of the quantity of second bits with respective physical levels of the four or more physical levels.

16 . The non-transitory computer-readable medium of claim 15 , wherein the instructions are further executable by the processing circuitry to:
perform the half-rate calculation at one or more processors based at least in part on combining respective quantities of first bits associated with respective portions of the signal to generate the quantity of second bits.

17 . The non-transitory computer-readable medium of claim 15 , wherein the instructions are further executable by the processing circuitry to:
generate the respective quantities of first bits based at least in part on performing one or more cyclic redundancy check operations on the respective portions of the signal, wherein identifying the respective quantities of first bits is based at least in part on generating the respective quantities of first bits.

18 . The non-transitory computer-readable medium of claim 15 , wherein the instructions are further executable by the processing circuitry to:
receive the signal as a burst transmission, wherein identifying the respective quantities of first bits is based at least in part on receiving the signal.

19 . The non-transitory computer-readable medium of claim 15 , wherein the instructions are further executable by the processing circuitry to:
convert a respective logic levels associated with the respective quantities of first bits to respective physical levels; and map the respective quantities of first bits to the respective physical levels based at least in part on converting the respective logic levels.

20 . The non-transitory computer-readable medium of claim 15 , wherein each respective quantity of first bits and the quantity of second bits comprises a same quantity of bits.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Dietrich Stefan
• Brox Martin
• Richter Michael Dieter
• Hein Thomas
• Schneider Ronny
• Jovanovic Natalija

Classifications

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title