Semiconductor device

Patent metadata

Field	Value
Publication number	US-2024405110-A1
Application number	US-202418806730-A
Country	US
Kind code	A1
Filing date	Aug 16, 2024
Priority date	Feb 18, 2022
Publication date	Dec 5, 2024
Grant date	—

Abstract

A semiconductor device includes a chip with a main surface, featuring a first conductivity type base region. A trench gate structure penetrates the base region, while a second conductivity type emitter region is formed along the trench gate structure on the surface. Between the bottom of the base region and the emitter region, a higher impurity concentration in-base region is present. An insulating film covers the main surface, featuring a connection hole that exposes part of the emitter region at a distance from the in-base region. A connection electrode is positioned in the connection hole, electrically connecting the base and emitter regions.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a chip that has a main surface; a first conductivity type base region that is formed in a surficial portion of the principal surface; a trench gate structure that is formed in the main surface so as to penetrate the base region; a second conductivity type emitter region that is formed in a region along the trench gate structure in a surficial portion of the base region; a first conductivity type in-base region that is formed in a region between a bottom portion of the base region and a bottom portion of the emitter region in the base region and that has an impurity concentration higher than the base region; an insulating film that covers the main surface and that has a connection hole that exposes a part of the emitter region at a distance from the in-base region in a direction along the main surface; and a connection electrode that is arranged in the connection hole so as to be electrically connected to the base region and to the emitter region.

2 . The semiconductor device according to claim 1 ,
wherein the in-base region is formed narrower than the emitter region.

3 . The semiconductor device according to claim 1 ,
wherein the connection hole intersects the trench gate structure in a plan view, and the connection electrode intersects the trench gate structure in a plan view.

4 . The semiconductor device according to claim 1 , further comprising:
a recess portion that is formed in the main surface so as to expose the emitter region; wherein the connection hole communicates with the recess portion, and the connection electrode includes a portion located in the connection hole and a portion located in the recess portion.

5 . The semiconductor device according to claim 4 ,
wherein the recess portion has a bottom wall placed closer to a side of the main surface than the bottom portion of the base region.

6 . The semiconductor device according to claim 5 ,
wherein a bottom wall of the recess portion is placed closer to the side of the main surface than the bottom portion of the emitter region.

7 . The semiconductor device according to claim 1 ,
wherein the in-base region is connected to the emitter region.

8 . The semiconductor device according to claim 1 ,
wherein the in-base region is formed at a distance from the emitter region toward a side of the bottom of the base region.

9 . The semiconductor device according to claim 1 ,
wherein the in-base regions are formed at a distance from each other in a thickness direction of the chip.

10 . The semiconductor device according to claim 1 ,
wherein the in-base region is formed in a whole area of a thickness range between the bottom portion of the base region and the bottom portion of the emitter region.

11 . The semiconductor device according to claim 1 , further comprising:
a first conductivity type second in-base region that is formed in the base region so as to be exposed from the connection hole and that has an impurity concentration higher than the base region; wherein the connection electrode is electrically connected to the second in-base region in the connection hole.

12 . The semiconductor device according to claim 11 ,
wherein the second in-base region is formed at a distance from the in-base region.

13 . The semiconductor device according to claim 1 ,
wherein the trench gate structure includes a trench formed in the main surface, a gate insulating film covering a wall surface of the trench, a gate embedded electrode embedded in the trench with the gate insulating film between the gate embedded electrode and the trench, an electrode recess portion formed at an electrode surface of the gate embedded electrode, and a recess insulator covering the electrode recess portion, the insulating film covers the gate embedded electrode, and has the connection hole that exposes the recess insulator, and the connection electrode has a portion facing the gate embedded electrode across the recess insulator in the connection hole.

14 . The semiconductor device according to claim 13 ,
wherein the in-base region is formed at a distance from the recess insulator.

15 . The semiconductor device according to claim 13 ,
wherein the connection hole exposes the emitter region and the recess insulator.

16 . The semiconductor device according to claim 13 ,
wherein the recess insulator has a portion that faces the base region along a surface direction of the main surface.

17 . The semiconductor device according to claim 13 ,
wherein the recess insulator has an embedded portion placed closer to a side of a bottom wall of the trench than the main surface and a projection portion placed higher than the main surface in a cross-sectional view.

18 . The semiconductor device according to claim 13 ,
wherein the insulating film has an insulating main surface placed higher than an upper end portion of the recess insulator.

19 . The semiconductor device according to claim 1 , further comprising:
a terminal electrode that is formed integrally with the connection electrode and that covers the insulating film.

20 . The semiconductor device according to claim 1 , further comprising:
a terminal electrode that is formed structurally independently of the connection electrode and that covers the insulating film and the connection electrode.

Assignees

• Rohm Co Ltd

Inventors

• Osawa Takayuki

Classifications

• H10D62/103

  for increasing or controlling the breakdown voltage of reverse-biased devices · CPC title

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H10D8/50

  PIN diodes · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D12/00

  Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT] · CPC title