Air gaps in memory array structures

Patent metadata

Field	Value
Publication number	US-2024404875-A1
Application number	US-202418770730-A
Country	US
Kind code	A1
Filing date	Jul 12, 2024
Priority date	Jun 26, 2020
Publication date	Dec 5, 2024
Grant date	—

Abstract

A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

First claim

What is claimed is:

1 . A method comprising:
forming a first word line extending over a semiconductor substrate; forming a sacrificial layer extending on the first word line; forming a second word line extending on the sacrificial layer; forming a memory film extending on the first word line and the second word line; forming a channel layer extending on the memory film; forming a source line extending on the channel layer; forming a bit line extending on the channel layer, wherein the bit line is separated from the source line by a first isolation region; and removing the sacrificial layer to form a first air gap extending between the first word line and the second word line.

2 . The method of claim 1 further comprising forming a second isolation region over the first word line, the sacrificial layer, and the second word line.

3 . The method of claim 2 , wherein removing the sacrificial layer comprises:
etching an opening in the second isolation region to expose the sacrificial layer; and etching the sacrificial layer through the opening.

4 . The method of claim 1 further comprising depositing a dielectric material on the first word line to form a seal that seals the first air gap.

5 . The method of claim 4 further comprising forming a conductive feature in the seal that contacts the first word line.

6 . The method of claim 4 , wherein the seal has a convex sidewall facing the first air gap.

7 . The method of claim 1 , wherein the first air gap has a height in the range of 20 nm to 80 nm.

8 . The method of claim 1 , wherein a central region of the first air gap has a smaller height than end regions of the first air gap.

9 . A method comprising:
depositing alternating layers of conductive material and sacrificial material to form a multi-layer stack; depositing a memory film along a sidewall of the multi-layer stack; depositing an oxide semiconductor (OS) layer over the memory film; forming an inter-metal dielectric layer (IMD) over the multi-layer stack; etching the IMD to expose each layer of sacrificial material; performing an etching process to remove each layer of sacrificial material and expose each layer of conductive material; depositing a dielectric material on each layer of conductive material to form an air gap on each layer of conductive material, wherein the dielectric material seals each air gap; etching openings in the dielectric material to expose each layer of conductive material; and depositing a conductive material in each opening.

10 . The method of claim 9 , wherein the dielectric material still seals each air gap after etching openings in the dielectric material.

11 . The method of claim 9 , wherein the dielectric material is silicon oxide.

12 . The method of claim 9 , wherein the sacrificial material is silicon.

13 . The method of claim 9 , wherein etching the IMD comprises etching openings through the IMD that each expose a respective layer of sacrificial material.

14 . The method of claim 9 , wherein each air gap has an end that is flush with an end of the layer of conductive material respectively underlying that air gap.

15 . A device comprising:
a vertical stack of gate electrodes over a substrate, wherein an respective air gap is sandwiched between respective gate electrodes of the vertical stack of gate electrodes; a ferroelectric material on a sidewall of vertical stack of gate electrodes; a channel material on the ferroelectric material; a source line on the channel material; a bit line on the channel material; and an insulating material on the channel material, wherein the insulating material separates the source line and the bit line.

16 . The device of claim 15 further comprising a plurality of first seals, wherein each first seal seals a first end of each respective air gap.

17 . The device of claim 16 further comprising a plurality of second seals, wherein each second seal seals a second end of each respective air gap.

18 . The device of claim 15 , wherein source line and the bit line each have an oval-shaped cross-section in a plan view.

19 . The device of claim 15 , wherein the source line and the bit line each have a flat sidewall and a rounded sidewall in a plan view.

20 . The device of claim 15 , wherein the ferroelectric material encircles the source line and the bit line, wherein the ferroelectric material is oval-shaped in a plan view.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Sheng-Chen
• LEE Kai-Hsuan
• Yeong Sai-Hooi
• Yu Chia-Ta
• Chia Han-Jong

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title