Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2024395923-A1
Application number	US-202318529864-A
Country	US
Kind code	A1
Filing date	Dec 5, 2023
Priority date	May 22, 2023
Publication date	Nov 28, 2024
Grant date	—

Abstract

Provided are a semiconductor device and a method of manufacturing the same, the semiconductor device including a substrate, a buffer layer on the substrate, an n-type epitaxial layer on the buffer layer, a protective layer on the n-type epitaxial layer, a p type layer disposed in a trench structure on the protective layer, and penetrating the protective layer and within the n-type epitaxial layer, a gate insulating layer on the p type layer, and a gate electrode on the gate insulating layer.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; a buffer layer on the substrate; an n-type epitaxial layer on the buffer layer; a protective layer on the n-type epitaxial layer; a p type layer disposed in a trench structure on the protective layer, and penetrating the protective layer and within the n-type epitaxial layer; a gate insulating layer on the p type layer; and a gate electrode on the gate insulating layer.

2 . The semiconductor device of claim 1 , wherein
the semiconductor device further includes an n+ type epitaxial layer on the n-type epitaxial layer; a source electrode on the n+ type epitaxial layer and the protective layer; and a drain electrode on the n+ type epitaxial layer and the protective layer.

3 . The semiconductor device of claim 1 , wherein
the p type layer includes NiO X (0.98≤x≤1).

4 . The semiconductor device of claim 1 , wherein
the buffer layer includes unintentionally doped (UID) gallium oxide.

5 . The semiconductor device of claim 1 , wherein
the n-type epitaxial layer includes n-type gallium oxide.

6 . The semiconductor device of claim 5 , wherein
the n-type epitaxial layer has a concentration of 1E16 cm −3 to 1E19 cm −3 .

7 . The semiconductor device of claim 1 , wherein
the protective layer includes SiO 2 , Si 2 N 3 , or a combination thereof.

8 . The semiconductor device of claim 1 , wherein
the gate insulating layer includes Al 2 O 3 , SiO 2 , HfO 2 , Si 2 N 3 or a combination thereof.

9 . The semiconductor device of claim 2 , wherein
the n+ type epitaxial layer includes n+ type gallium oxide.

10 . A method of manufacturing a semiconductor device, comprising:
sequentially forming a buffer layer and an n-type epitaxial layer on a substrate; forming a protective layer on the n-type epitaxial layer; etching the protective layer and etching a portion of the n-type epitaxial layer through the protective layer to form a trench structure; forming a p type layer on the protective layer and the n-type epitaxial layer along the trench structure; forming a gate insulating layer on the p type layer; and forming a gate electrode on the gate insulating layer.

11 . The method of claim 10 , wherein
the forming of the p type layer, the gate insulating layer, and the gate electrode is performed by a lift-off process or an etching process.

12 . The method of claim 10 , wherein
the method further includes forming and etching an n+ type epitaxial layer on the n-type epitaxial layer before the forming of a protective layer on the n-type epitaxial layer, and the protective layer is formed on the n+ type epitaxial layer and the n-type epitaxial layer.

13 . The method of claim 12 , wherein
after the forming of the gate electrode, the method further includes forming a source electrode and a drain electrode on the n+ type epitaxial layer and the protective layer.

14 . The method of claim 13 , wherein
after the forming of the gate electrode, the forming of the source electrode and the drain electrode is performed by a lift-off process or an etching process.

15 . The method of claim 12 , wherein
at the same time as forming the gate electrode, the method further includes forming a source electrode and a drain electrode on the n+ type epitaxial layer and the protective layer.

16 . The method of claim 15 , wherein
at the same time as forming the gate electrode, the forming of the source electrode and the drain electrode includes sequentially depositing a gate electrode material, a source electrode material, and a drain electrode material on the gate insulating layer and performing a lift-off process or an etching process.

17 . The method of claim 10 , wherein
the p type layer includes NiO X (0.98≤x≤1).

Assignees

• Hyundai Motor Co Ltd
• Kia Corp

Inventors

• Chun Dae Hwan
• Park Junghee
• Hong Jungyeop
• Kim Taehyun
• Jung Youngkyun
• Joo Nackyong

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D64/027

  by etching at gate locations · CPC title

• H10D62/80 Primary

  characterised by the materials · CPC title