Semiconductor device and method manufacturing the same

Patent metadata

Field	Value
Publication number	US-2023045172-A1
Application number	US-202217663866-A
Country	US
Kind code	A1
Filing date	May 18, 2022
Priority date	Jul 29, 2021
Publication date	Feb 9, 2023
Grant date	—

Abstract

A semiconductor device includes an N+ type substrate, an N− type layer disposed on a first surface of the N+ type substrate and having a trench opened to a surface opposite to the surface facing the N+ type substrate, a P type region disposed in the N− type layer and disposed on a side surface of the trench, a gate electrode disposed in the trench, and a source electrode and a drain electrode insulated from the gate electrode. The N− type layer includes a P type shield region covering a bottom surface and an edge of the trench.

First claim

What is claimed is:

1 . A semiconductor device, comprising
an N+ type substrate; an N− type layer disposed on a first surface of the N+ type substrate and having a trench opened to a surface opposite to the surface facing the N+ type substrate; a P type region disposed in the N− type layer and disposed on a side surface of the trench; a gate electrode disposed in the trench; and a source electrode and a drain electrode insulated from the gate electrode, wherein the N− type layer includes a P type shield region covering a bottom surface and an edge of the trench.

2 . The semiconductor device of claim 1 , wherein
the N− type layer includes an N type current diffusion region disposed on a side surface of the trench.

3 . The semiconductor device of claim 2 , wherein
the N type current diffusion region is disposed on the P type shield region.

4 . The semiconductor device of claim 2 , wherein
the P type shield region and the N type current diffusion region are connected to each other to cover the bottom and side surfaces of the trench.

5 . The semiconductor device of claim 2 , wherein
the trench includes a first trench region disposed in the P type region and having a first width, and a second trench region disposed in the N− type layer and having a second width, wherein the first width of the first trench region is wider than the second width of the second trench region.

6 . The semiconductor device of claim 5 , wherein
the first width of the first trench region is the same as a width of the P type shield region.

7 . The semiconductor device of claim 5 , wherein
a bottom surface of the first trench region having the first width is disposed in the P type region and not in the N− type layer.

8 . The semiconductor device of claim 5 , wherein
the second width of the second trench region is narrower than a width of the P type shield region.

9 . The semiconductor device of claim 5 , wherein
a bottom surface of the second trench region having the second width passes through the N type current diffusion region and is disposed in the P type shield region.

10 . The semiconductor device of claim 5 , wherein
the N type current diffusion region is disposed under a bottom surface of the first trench region having a first width, a side surface of the second trench region having a second width, and on an upper portion of the P type shield region.

11 . The semiconductor device of claim 5 , wherein
the gate electrode has a third width in the P type region and a fourth width in the N− type layer, and the third width of the gate electrode is wider than the fourth width.

12 . The semiconductor device of claim 1 , wherein
the semiconductor device further includes a first insulating layer disposed between the trench and the gate electrode.

13 . The semiconductor device of claim 1 , wherein
the gate electrode includes a first gate electrode region disposed in the trench and a second gate electrode region protruding above the trench.

14 . The semiconductor device of claim 13 , wherein
the semiconductor device further includes a second insulating layer covering the second gate electrode region protruding above the trench.

15 . The semiconductor device of claim 1 , wherein
the source electrode is disposed on the N− type layer, and the drain electrode is disposed on a second surface of the substrate.

16 . A method of manufacturing a semiconductor device, comprising
forming an N− type layer on a first surface of an N+ type substrate; forming a P type region in the N− type layer; implanting P type ions with a first width into the N− type layer and the P type region to form a P type ion implantation region; implanting N type ions with a first width to a partial depth of the P type ion implantation region to form an N type ion implantation region and a P type shield region under the N type ion implantation region; etching the N type ion implantation region and the P type shield region to form a trench; forming a gate electrode inside the trench; and forming a source electrode and a drain electrode to be insulated from the gate electrode, respectively.

17 . The method of claim 16 , wherein
the forming of the P type ion implantation region includes forming a first mask having an opening of a first width on the P type region, and then using the first mask, implanting P type ions into the N− type layer and the P type region with a first width to form a P type ion implantation region.

18 . The method of claim 16 , wherein
the forming of the P type shield region is performed by using an ion doping neutralization (compensation) method.

19 . The method of claim 18 , wherein
a difference between an amount of N type ions implanted to form the N type ion implantation region and an amount of P type ions implanted to form the P type ion implantation region is greater than an ion implantation concentration of the N− type layer.

20 . The method of claim 17 , wherein
the forming of the trench includes etching the N type ion implantation region to a partial depth using a first mask to form a first trench region having a first width.

21 . The method of claim 20 , wherein
the etching of the N type ion implantation region is performed such that a bottom surface of the first trench region having the first width is disposed in the P type region and not in the N− type layer.

22 . The method of claim 20 , wherein
the forming of the trench includes forming a second mask having an opening having a second width on a side surface of the first trench region, and then using the second mask, etching the P type shield region to a partial depth penetrating the N type ion implantation region to form a second trench region having a second width.

23 . The method of claim 22 , wherein
the etching of the P type shield region is performed such that a bottom surface of the second trench region having the second width passes through the N type current diffusion region and is disposed in the P type shield region.

24 . The method of claim 23 , wherein
the method of manufacturing the semiconductor device further includes forming a first insulating layer on the bottom and side surfaces of the second trench region, the bottom and side surfaces of the first trench region, and the P type region.

25 . The method of claim 16 , wherein
the method of manufacturing the semiconductor device further includes forming a second insulating layer on the gate electrode after forming the gate electrode in the trench.

26 . The method of claim 16 , wherein
the method of manufacturing the semiconductor device further includes forming an N+ type region disposed in the P type region and disposed on a side surface of the trench.

27 . The method of claim 16 , wherein
the method of manufacturing the semiconductor device further includes forming a source electrode on the P type region to be insulated from the gate electrode.

28 . The method of claim 16 , wherein
the method of manufacturing the semiconductor device further includes forming a drain electrode on the second surface of the substrate.

Assignees

• Hyundai Motor Co Ltd
• Kia Corp

Inventors

• Joo Nackyong
• Chun Dae Hwan
• Hong Jungyeop
• Jung Youngkyun
• Park Junghee

Classifications

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D62/8325

  Silicon carbide · CPC title