Semiconductor device including backside source/drain contact structure with contact spacer and backside gate contact structure

Patent metadata

Field	Value
Publication number	US-2024395900-A1
Application number	US-202318380951-A
Country	US
Kind code	A1
Filing date	Oct 17, 2023
Priority date	May 25, 2023
Publication date	Nov 28, 2024
Grant date	—

Abstract

A semiconductor device includes: a 1 st source/drain region; a 2 nd source/drain region; a channel structure connecting the 1 st source/drain region to the 2 nd source/drain region; a gate structure configured to control the channel structure; a backside source/drain contact structure connected to a bottom surface of the 1 st source/drain region; a backside isolation structure at a lower portion of the semiconductor device; and a 1 st contact spacer on the backside source/drain contact structure, wherein the 1 st contact spacer is configured to isolate the backside source/drain contact structure from another circuit element in the backside isolation structure.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a 1 st source/drain region; a 2 nd source/drain region; a channel structure connecting the 1 st source/drain region to the 2 nd source/drain region; a gate structure configured to control the channel structure; a backside isolation structure at a lower portion of the semiconductor device; a backside source/drain contact structure connected to a bottom surface of the 1 st source/drain region in the backside isolation structure; a 1 st contact spacer on the backside source/drain contact structure, wherein the 1 st contact spacer is configured to isolate the backside source/drain contact structure from another circuit element in the backside isolation structure.

2 . The semiconductor device of claim 1 , wherein the 1 st contact spacer is foremd on a side surface of the backside source/drain contact structure, and comprises an isolatin material.

3 . The semiconductor device of claim 1 , further comprising:
a backside gate contact structure connected to a bottom surface of the gate structure.

4 . The semiconductor device of claim 3 , wherein the backside isolation structure is formed between the backside gate contact structure and the 1 st contact spacer.

5 . The semiconductor device of claim 3 , wherein the backside gate contact structure contacts the 1 st contact spacer.

6 . The semiconductor device of claim 1 , further comrpising:
a placeholder structure connected to a bottom surface of the 2 nd source/drain region; and a 2 nd contact spacer on the placeholder structure, the 2 nd contact spacer isolating the placeholder structure from another circuit element in the backside isolation structure.

7 . The semiconductor device of clam 6 , wherein the 2 nd contact spacer comprises:
a side spacer on a side surface of the placeholder structure; and a bottom spacer on a bottom surface of the placeholder structure.

8 . The semiconductor device of claim 6 , further comprising a ftontside source/drain contact structure conneced to the 2 nd source/drain region.

9 . The semiconductor device of claim 6 , further comrpising:
a backside gate contact structure connected to a bottom surface of the gate structure.

10 . The semiconductor device of claim 9 , wherein the backside gate contact structure is formed between the 1 st contact spacer and the 2 nd contact spacer.

11 . A semiconductor device comprising:
a 1 st source/drain region; a 2 nd source/drain region; a channel structure connecting the 1 st source/drain region to the 2 nd source/drain region; a gate structure configured to control the channel structure; a backside isolation structure at a lower portion of the semiconductor device; and a backside gate contact structure connected to a bottom surface of the gate structure in the backside isolation structure, wherein the backside gate contact structure is misligned with the bottom surface of the gate structure to be closer to the 2 nd source/drain region than the 1 st source/drain region.

12 . The semiconductor device of claim 11 , wherein a portion of the backside gate contact structure does not contact the bottom surface of the gate structure.

13 . The semiconductor device of claim 12 , wherein the portion of the backside gate contact structure that does not contact the bottom surface of the gate structure contacts a bottom surface of an inner spacer formed between the gate structure and the 1 st source/drain region.

14 . The semiconductor device of claim 12 , wherein the backside gate contact structure is formed to be closer to the 1 st source/drain region than the 2 nd source/drain region.

15 . The semiconductor device of claim 11 , further comprising:
a backside source/drain contact structure connected to a bottom surface of the 1 st source/drain region; and a 1 st contact spacer on the backside source/drain contact structure, the 1 st contact spacer configured to isolate the backside source/drain contact structure from another circuit element in the backside isolation structure.

16 . The semiconductor device of claim 13 , wherein the backside gate contact structure contacts the 1 st contact spacer.

17 . The semiconductor device of claim 16 , further comrpising:
a placeholder structure connected to a bottom surface of the 2 nd source/drain region; and a 2 nd contact spacer on the placeholder structure, the 2 nd contact spacer isolating the placeholder structure from another circuit element in the backside isolation structure.

18 . The semiconductor device of claim 17 , further comprising a ftontside source/drain contact structure conneced to the 2 nd source/drain region.

19 . A method of manufacturing a semiconductor device, comprising:
forming a placeholder structure on a bottom surface of a source/drain region; forming a contact spacer on the placeholder structure; forming a backside gate contact structure on a bottom surface of a gate structure; and replacing the placeholder structure with a backside source/drain contact structure such that the backside source/drain contact structure is surrounded by the contact spacer.

20 . The method of claim 19 , wherein the backside gate contact structure is formed to contact the contact spacer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yun Seungchan
• Martineau Jason
• Seo Kang-Ill

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D30/0198

  forming source or drain electrodes wherein semiconductor bodies are replaced by dielectric layers and the source or drain electrodes extend through the dielectric layers · CPC title

• H10D84/834

  comprising FinFETs · CPC title