Offset cancellation

Patent metadata

Field	Value
Publication number	US-2024395299-A1
Application number	US-202418736326-A
Country	US
Kind code	A1
Filing date	Jun 6, 2024
Priority date	Oct 16, 2018
Publication date	Nov 28, 2024
Grant date	—

Abstract

Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.

First claim

1 . (canceled)

2 . A method for memory operations, comprising:
communicating, as part of a calibration procedure, one or more calibration signals over a channel; calibrating a plurality of data eyes based at least in part on communicating the one or more calibration signals, the plurality of data eyes being associated with communications according to a pulse amplitude modulation (PAM) signaling scheme; and communicating, over the channel, a first signal according to the PAM signaling scheme based at least in part on calibrating the plurality of data eyes.

3 . The method of claim 2 , wherein calibrating the plurality of data eyes comprises:
calibrating a respective reference voltage level for each of the plurality of data eyes.

4 . The method of claim 2 , wherein communicating the first signal according to the PAM signaling scheme comprises:
communicating a plurality of symbols, wherein each symbol of the plurality of symbols represents two bits of data.

5 . The method of claim 2 , wherein communicating the first signal according to the PAM signaling scheme comprises:
communicating a first voltage level of three voltage levels, wherein each of the three voltage levels represent two bits of data.

6 . The method of claim 2 , wherein the PAM signaling scheme is associated with high-speed data transmissions.

7 . The method of claim 2 , wherein the channel is actively terminated during the communication of the first signal, and the channel is actively terminated at a high level or a low level.

8 . A non-transitory computer-readable medium storing code for memory operations, the code comprising instructions executable by one or more processors to:
communicate, as part of a calibration procedure, one or more calibration signals over a channel; calibrate a plurality of data eyes based at least in part on communicating the one or more calibration signals, the plurality of data eyes being associated with communications according to a pulse amplitude modulation (PAM) signaling scheme; and communicate, over the channel, a first signal according to the PAM signaling scheme based at least in part on calibrating the plurality of data eyes.

9 . The non-transitory computer-readable medium of claim 8 , wherein the instructions to calibrate the plurality of data eyes are executable by the one or more processors to:
calibrate a respective reference voltage level for each of the plurality of data eyes.

10 . The non-transitory computer-readable medium of claim 8 , wherein the instructions to communicate the first signal according to the PAM signaling scheme are executable by the one or more processors to:
communicate a plurality of symbols, wherein each symbol of the plurality of symbols represents two bits of data.

11 . The non-transitory computer-readable medium of claim 8 , wherein the instructions to communicate the first signal according to the PAM signaling scheme are executable by the one or more processors to:
communicate a first voltage level of three voltage levels, wherein each of the three voltage levels represent two bits of data.

12 . The non-transitory computer-readable medium of claim 8 , wherein the PAM signaling scheme is associated with high-speed data transmissions.

13 . The non-transitory computer-readable medium of claim 8 , wherein the channel is actively terminated during the communication of the first signal, and the channel is actively terminated at a high level or a low level.

14 . An apparatus, comprising:
one or more memories; and one or more processors coupled with the one or more memories and configured to cause the apparatus to:
communicate, as part of a calibration procedure, one or more calibration signals over a channel;
calibrate a plurality of data eyes based at least in part on communicating the one or more calibration signals, the plurality of data eyes being associated with communications according to a pulse amplitude modulation (PAM) signaling scheme; and
communicate, over the channel, a first signal according to the PAM signaling scheme based at least in part on calibrating the plurality of data eyes.

15 . The apparatus of claim 14 , wherein, to calibrate the plurality of data eyes, the one or more processors are configured to cause the apparatus to:
calibrate a respective reference voltage level for each of the plurality of data eyes.

16 . The apparatus of claim 14 , wherein, to communicate the first signal according to the PAM signaling scheme, the one or more processors are configured to cause the apparatus to:
communicate a plurality of symbols, wherein each symbol of the plurality of symbols represents at least two bits of data.

17 . The apparatus of claim 14 , wherein, to communicate the first signal according to the PAM signaling scheme, the one or more processors are configured to cause the apparatus to:
communicate a first voltage level of three voltage levels, wherein each of the three voltage levels represent at least two bits of data.

18 . The apparatus of claim 14 , wherein the PAM signaling scheme is associated with high-speed data transmissions.

19 . The apparatus of claim 14 , wherein the channel is actively terminated during the communication of the first signal, and the channel is actively terminated at a high level or a low level.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Brox Martin
• Spirkl Wolfgang Anton
• Hein Thomas
• Richter Michael Dieter
• Mayer Peter

Classifications

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/225 Primary

  Auxiliary circuits · CPC title

• G06F13/4086

  Bus impedance matching, e.g. termination · CPC title

• G11C7/109

  Control signal input circuits · CPC title