Ruthenium-based liner for a copper interconnect

Patent metadata

Field	Value
Publication number	US-2024387256-A1
Application number	US-202418787735-A
Country	US
Kind code	A1
Filing date	Jul 29, 2024
Priority date	Aug 30, 2021
Publication date	Nov 21, 2024
Grant date	—

Abstract

In some implementations, one or more semiconductor processing tools may form a via within a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a ruthenium-based liner within the via. The one or more semiconductor processing tools may deposit, after depositing the ruthenium-based liner, a copper plug within the via.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, comprising:
forming a via within a substrate of the semiconductor device; depositing a first liner comprising a first material within the via; depositing a second liner comprising a second material on the first liner within the via; depositing a third liner comprising a metal material on the second liner within the via; depositing a plug comprising a third material on the third liner within the via; and depositing a cap comprising the second material directly on an upper surface of the plug, an upper surface of the third liner, and an upper surface of the second liner.

2 . The method of claim 1 , wherein the cap is deposited within the via.

3 . The method of claim 1 , further comprising:
depositing another cap comprising the metal material directly on an upper surface of the cap and an upper surface of the first liner.

4 . The method of claim 3 , wherein the other cap is deposited within the via.

5 . The method of claim 1 , wherein the first material is a tantalum nitride-based material.

6 . The method of claim 1 , wherein the second material is a ruthenium-based material.

7 . The method of claim 1 , wherein the metal material is a cobalt-based material.

8 . A semiconductor device, comprising:
a via within a substrate of the semiconductor device; a first liner comprising a first material disposed within the via; a second liner comprising a second material disposed on the first liner within the via; a third liner comprising a metal material on the second liner within the via; a plug comprising a third material disposed on the third liner within the via; and a cap comprising the second material disposed directly on an upper surface of the plug, an upper surface of the third liner, and an upper surface of the second liner.

9 . The semiconductor device of claim 8 , wherein the cap is disposed within the via.

10 . The semiconductor device of claim 8 , further comprising:
another cap comprising the metal material disposed directly on an upper surface of the cap and an upper surface of the first liner.

11 . The semiconductor device of claim 8 , wherein the other cap is deposited within the via.

12 . The semiconductor device of claim 8 , wherein the first material is a tantalum nitride-based material.

13 . The semiconductor device of claim 8 , wherein the second material is a ruthenium-based material.

14 . The semiconductor device of claim 8 , wherein the metal material is a cobalt-based material.

15 . A method of manufacturing a semiconductor device, comprising:
forming a via within a substrate of the semiconductor device; depositing a first liner comprising a first material on the substrate; depositing a second liner comprising a second material on the first liner; depositing a third liner comprising a third material on the second liner; depositing a fourth material on the third liner; planarizing, after depositing the fourth material, the semiconductor device; and depositing a cap comprising the second material directly on an upper surface of the fourth material, an upper surface of the third liner, and an upper surface of the second liner.

16 . The method of claim 15 , wherein planarizing the semiconductor device comprises at least one of:
removing a portion of the first liner outside of the via; removing a portion of the second liner outside of the via; removing a portion of the third liner outside of the via; or removing a portion of the fourth material outside of the via.

17 . The method of claim 15 , wherein the cap is deposited within the via.

18 . The method of claim 15 , further comprising:
depositing another cap comprising the third material directly on an upper surface of the cap and an upper surface of the first liner.

19 . The method of claim 18 , wherein the other cap is deposited within the via.

20 . The method of claim 15 , comprises:
forming an interconnect within the via based on planarizing the semiconductor device.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Yao-Min
• Gao ming-yuan
• Chiang Ming-Chou
• Chin Shu-Cheng
• Hsieh Huei-Wen
• Kuo Kai-Shiang
• Lin Yen-Chun
• Weng Cheng-Hui
• Lin Chun-Chieh
• Su Hung-Wen

Classifications

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title