Vertical 2-transistor memory cell

Patent metadata

Field	Value
Publication number	US-2024373619-A1
Application number	US-202418662659-A
Country	US
Kind code	A1
Filing date	May 13, 2024
Priority date	Dec 26, 2018
Publication date	Nov 7, 2024
Grant date	—

Abstract

Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.

First claim

1 . An apparatus comprising:
a first transistor of a memory cell, the first transistor including a first region; a second transistor of the memory cell, the second transistor including a second region separated from the first region; a memory element of the memory cell, the memory element including a first portion and a second portion, the first portion located on a first side of the first region of the first transistor and separated from the first side of the first region by a first dielectric material, the second portion located on a second side of the first region of the first transistor and separated from the second side of the first region by a second dielectric material; a first conductive portion coupling the second region of the second transistor to the first portion and the second portion of the memory element; and a second conductive portion coupling the second region of the second transistor to the second portion of the memory element.

2 . The apparatus of claim 1 , further comprising:
a first conductive region contacting the second region of the second transistor, wherein the second region is between the second conductive region and the third conductive region.

3 . The apparatus of claim 2 , further comprising:
a third conductive region contacting the first region of the first transistor; and a second conductive region contacting the first region of the first transistor, wherein the first region is between the first conductive region and the second conductive region.

4 . The apparatus of claim 1 , further comprising:
a conductive region adjacent a first side of first region of the first transistor, a first side of the first portion of the memory element, and a first side of the second portion of the memory element; and a dielectric material between the conductive region and the first side of each of the first region of the first transistor, the first portion of the memory element, and the second portion of the memory element.

5 . The apparatus of claim 4 , further comprising:
an additional conductive region adjacent a second side of first region of the first transistor, a second side of the first portion of the memory element, and a second side of the second portion of the memory element; and an additional dielectric material between the additional conductive region and the second side of each of the first region of the first transistor, the first portion of the memory element, and the second portion of the memory element.

6 . The apparatus of claim 1 , further comprising:
a conductive region adjacent a first side of second region of the second transistor, a first side of the first portion of the memory element, and a first side of the second portion of the memory element; and a dielectric material between the conductive region and the first side of each of the second region of the second transistor, the first portion of the memory element, and the second portion of the memory element.

7 . The apparatus of claim 4 , further comprising:
an additional conductive region adjacent a second side of second region of the second transistor, a second side of the first portion of the memory element, and a second side of the second portion of the memory element; and an additional dielectric material between the additional conductive region and the second side of each of the second region of the second transistor, the first portion of the memory element, and the second portion of the memory element.

8 . An apparatus comprising:
a first transistor of a memory cell, the first transistor including a first region; a second transistor of the memory cell, the second transistor including a second region located separated from the first region by a first dielectric material; a conductive region between the first region of the first transistor and the second region of the second transistor; a memory element of the memory cell located on at least one side of the first region of the first transistor and separated from the first region by a second dielectric material; and a conductive coupling contacting the second region of the second transistor and the memory element.

9 . The apparatus of claim 8 , wherein the memory element includes polysilicon.

10 . The apparatus of claim 8 , wherein the conductive coupling includes metal.

11 . The apparatus of claim 8 , wherein first region includes a piece of semiconductor material.

12 . The apparatus of claim 8 , wherein the first region includes a piece of metal.

13 . The apparatus of claim 8 , wherein the second region includes a piece of oxide material.

14 . The apparatus of claim 8 , wherein the second region includes a piece of oxide material, and the memory element includes a piece of polysilicon contacting the piece of oxide material.

15 . The apparatus of claim 8 , further comprising, an additional conductive region contacting the first region of the first transistor, wherein the first region of the first transistor is between the conductive region and the additional conductive region.

16 . The apparatus of claim 8 , further comprising, an additional conductive region contacting the second region of the second transistor, wherein the second region of the second transistor is between the conductive region and the additional conductive region.

17 . An apparatus comprising:
a conductive region; a first memory cell adjacent the conductive region, the fist memory cell including a first transistor and a second transistor adjacent the first transistor; a second memory cell adjacent the conductive region, the second memory cell including a first transistor and a second transistor located adjacent the first transistor of second memory cell; a third memory cell adjacent the conductive region, the third memory cell including a first transistor a second transistor adjacent the first transistor of third memory cell; a first conductive structure between the first and second memory cells, the first conductive structure contacting the conductive region; and a second conductive structure between the second and third memory cells, the second conductive structure contacting the conductive region.

18 . The apparatus of claim 17 , wherein each of the first, second, and third memory cells includes a memory element, and wherein:
the first conductive structure is between the memory element of the first memory cell and the memory element of the second memory cell; and the second conductive structure is between the memory element of the second memory cell and the memory element of the third memory cell.

19 . The apparatus of claim 17 , wherein the second transistors of each of the first, second, and third memory cells includes a channel region coupled to the memory element of a respective memory cell of the first, second, and third memory cells.

20 . The apparatus of claim 19 , wherein the first transistors of each of the first, second, and third memory cells includes a channel region, and the memory element of each of the first, second, and third memory cells includes:
a first portion adjacent a first side of the channel region of a respective memory cell of the first, second, and third memory cells, and a second portion adjacent a second side of the channel region of a respective memory cell of the first, second, and third memory cells.

Assignees

• Micron Technology Inc

Inventors

• Karda Kamal M
• Pulugurtha Srinivas
• Liu Haitao
• Sarpatwari Karthik
• Ramaswamy Durai Vishak Nirmal

Classifications

• G11C11/4023

  using field effect transistors · CPC title

• H10B12/01 Primary

  Manufacture or treatment · CPC title

• G11C11/403

  with charge regeneration common to a multiplicity of memory cells, i.e. external refresh · CPC title

• H10B12/20 Primary

  DRAM devices comprising floating-body transistors, e.g. floating-body cells · CPC title