Deep trench isolations and methods of forming the same

Patent metadata

Field	Value
Publication number	US-2024363671-A1
Application number	US-202418768642-A
Country	US
Kind code	A1
Filing date	Jul 10, 2024
Priority date	Aug 31, 2015
Publication date	Oct 31, 2024
Grant date	—

Abstract

A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

First claim

What is claimed is:

1 . A method comprising:
performing a first etching process on a semiconductor substrate to form a trench, wherein the trench comprises a rounded bottom, and wherein the first etching process is performed using first etching conditions; performing a second etching process to remove a surface layer of the semiconductor substrate, with the surface layer being exposed to the trench, wherein the rounded bottom of the trench is etched to form a slant-and-straight bottom surface, and wherein the second etching process is performed using second etching conditions different from the first etching conditions; and filling the trench to form a trench isolation region in the trench, wherein the filling the trench comprises depositing a first dielectric layer in the trench, and wherein the first dielectric layer has a bottom end higher than a top end of the slant-and-straight bottom surface.

2 . The method of claim 1 , wherein the first etching process comprises an anisotropic etching process, and the second etching process comprises an isotropic etching process.

3 . The method of claim 2 , wherein the first etching process comprises a dry etching process, and the second etching process comprises a wet etching process.

4 . The method of claim 2 further comprising performing a cleaning process between the first etching process and the second etching process.

5 . The method of claim 1 , wherein the second etching process is performed until the trench has a V-shaped bottom.

6 . The method of claim 1 , wherein the second etching process is performed until the trench has a U-shaped bottom.

7 . The method of claim 1 , wherein the slant-and-straight bottom surface is on a (111) plane of the semiconductor substrate.

8 . The method of claim 7 , wherein the slant-and-straight bottom surface on the (111) plane of the semiconductor substrate is joined to a top surface of the semiconductor substrate, with the top surface being at a bottom of the trench, and wherein the top surface is on a (001) plane of the semiconductor substrate.

9 . The method of claim 1 , wherein the filling the trench further comprises:
forming a conformal oxide layer extending into the trench, wherein the first dielectric layer is deposited over the conformal oxide layer.

10 . The method of claim 9 further comprising:
after the first dielectric layer is formed, filling a metal region into the trench; and
etching back the metal region.

11 . The method of claim 1 , wherein the depositing the first dielectric layer comprises depositing a high-k dielectric material.

12 . The method of claim 1 , wherein the filling the trench further comprises depositing a second dielectric layer over the first dielectric layer, wherein the second dielectric layer comprises a lower portion in the trench, and an upper portion out of the trench.

13 . The method of claim 1 , wherein the trench isolation region forms a grid.

14 . A method comprising:
etching a semiconductor substrate to form a trench; after the trench is formed, performing an etching process to remove a surface layer of the semiconductor substrate, with the surface layer being in the trench; and after the etching process, filling the trench to form a trench isolation region in the trench, wherein the filling the trench comprises:
forming a first layer extending into the trench;
forming a second layer over the first layer; and
etching back the second layer until a top surface of the second layer is lower than a top surface of the first layer.

15 . The method of claim 14 , wherein the forming the first layer comprises depositing a dielectric layer, and the forming the second layer comprises depositing a metallic material.

16 . The method of claim 14 , wherein before the etching process, the trench comprises a rounded bottom surface, and wherein after the etching process, the trench comprises a slant-and-straight bottom.

17 . The method of claim 16 , wherein forming the first layer comprises depositing a high-k dielectric layer comprising a lower portion in the trench, wherein the lower portion has gradually reduced widths in a direction pointing from a top end to a bottom end of the trench, and wherein the lower portion has a bottommost end higher than a topmost point of the slant-and-straight bottom.

18 . A method comprising:
performing a dry etching process on a semiconductor substrate to form a trench in the semiconductor substrate, wherein the trench comprises a vertical-and-straight edge and a rounded bottom surface joined to the vertical-and-straight edge; performing a wet etching process on a portion of the semiconductor substrate in the trench, wherein the wet etching process converts the rounded bottom surface into a slant-and-straight bottom joined to the vertical-and-straight edge; and filling the trench to form a trench isolation region in the trench, wherein the filling the trench comprises forming a plurality of layers, and wherein the forming the plurality of layers comprise depositing a high-k dielectric layer, wherein lower portions of the high-k dielectric layer are in the trench, and wherein a first bottom end of the lower portions of the high-k dielectric layer is higher than a second bottom end of the vertical-and-straight edge.

19 . The method of claim 18 , wherein the forming the plurality of layers comprises forming a core, and wherein the core is between opposing portions of the high-k dielectric layer in the trench.

20 . The method of claim 19 , wherein the forming the core comprises a deposition process and an etch-back process, and the forming the plurality of layers further comprises forming a recap dielectric layer over and contacting the core.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chou Cheng-Hsien
• Lai Chih-Yu
• Chou Shih Pei
• Chiang Yen-Ting
• Tseng Hsiao-Hui
• Tsai Min-Ying

Classifications

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/01

  Manufacture or treatment · CPC title

• H10W10/00 Primary

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title