Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2024363506-A1
Application number	US-202418594792-A
Country	US
Kind code	A1
Filing date	Mar 4, 2024
Priority date	Mar 14, 2016
Publication date	Oct 31, 2024
Grant date	—

Abstract

A thin semiconductor device with enhanced edge protection, and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a thin semiconductor device comprising a substrate with an edge-protection region, and a method of manufacturing thereof.

First claim

1 - 20 . (canceled)

21 . A semiconductor device, comprising:
a substrate comprising a substrate top side, a substrate bottom side, substrate lateral sides defining a perimeter of the substrate, a conductive structure at the perimeter of the substrate, and a mold material providing a portion of the substrate top side and a portion of the substrate bottom side; a semiconductor die coupled to the substrate top side; and an encapsulant that encapsulates the semiconductor die and contacts the mold material at the substrate top side; wherein the conductive structure comprises an upper portion and a lower portion adjoining the upper portion; wherein the upper portion of the conductive structure comprises an upper portion bottom side, an upper portion top side providing a portion of the substrate top side, and an upper portion lateral side exposed at the perimeter of the substrate; wherein the lower portion of the conductive structure comprises a lower portion bottom side providing a portion of the substrate bottom side and a lower portion lateral side exposed at the perimeter of the substrate; wherein the upper portion of the conductive structure is wider than the lower portion of the conductive structure; and wherein the mold material of the substrate contacts the upper portion bottom side.

22 . The semiconductor device of claim 21 , wherein the upper portion bottom side of the conductive structure adjoins a lower portion top side of the conductive structure.

23 . The semiconductor device of claim 21 , wherein:
the substrate comprises a conductive pattern at the substrate top side; and a bottom side of the semiconductor die is coupled to the conductive pattern.

24 . The semiconductor device of claim 21 , wherein:
the substrate comprises a conductive pattern at the substrate top side; and the semiconductor die is coupled to the conductive pattern.

25 . The semiconductor device of claim 24 , wherein the conductive pattern is coupled to the conductive structure.

26 . The semiconductor device of claim 24 , wherein the conductive pattern is isolated from the conductive structure.

27 . The semiconductor device of claim 21 , wherein a thickness of the lower portion of the conductive structure is greater than a thickness of the upper portion of the conductive structure.

28 . The semiconductor device of claim 21 , wherein the encapsulant covers a lateral side of semiconductor die and covers a top side of the semiconductor die.

29 . The semiconductor device of claim 21 , wherein the upper portion of the conductive structure and the lower portion of the conductive structure are a same metal.

30 . A semiconductor device, comprising:
a substrate comprising a substrate top side, a substrate bottom side, and substrate lateral sides defining a perimeter of the substrate; a semiconductor die coupled to the substrate top side; and an encapsulant that encapsulates the semiconductor die; wherein the perimeter of the substrate comprises a conductive structure; wherein an upper portion of the conductive structure comprises an upper portion bottom side, an upper portion top side exposed at the substrate top side, and an upper portion lateral side exposed at a first substrate lateral side of the substrate lateral sides; wherein a lower portion of the conductive structure adjoins the upper portion of the conductive structure and comprises a lower portion bottom side exposed at the substrate bottom side and a lower portion lateral side exposed at the first substrate lateral side; wherein the upper portion of the conductive structure is wider than the lower portion of the conductive structure; and wherein a mold material of the substrate contacts the upper portion bottom side of the conductive structure and contacts the encapsulant.

31 . The semiconductor device of claim 30 , wherein the upper portion bottom side of the conductive structure adjoins a lower portion top side of the conductive structure.

32 . The semiconductor device of claim 30 , wherein:
the substrate comprises a conductive pattern at the substrate top side; and a bottom side of the semiconductor die is coupled to the conductive pattern.

33 . The semiconductor device of claim 30 , wherein:
the substrate comprises a conductive pattern at the substrate top side; and the semiconductor die is coupled to the conductive pattern.

34 . The semiconductor device of claim 33 , wherein the conductive pattern is coupled to the conductive structure.

35 . The semiconductor device of claim 33 , wherein the conductive pattern is isolated from the conductive structure.

36 . The semiconductor device of claim 30 , wherein a thickness of the lower portion of the conductive structure is greater than a thickness of the upper portion of the conductive structure.

37 . The semiconductor device of claim 30 , wherein the encapsulant covers a lateral side of semiconductor die and covers a top side of the semiconductor die.

38 . The semiconductor device of claim 30 , wherein the upper portion of the conductive structure and the lower portion of the conductive structure are a same metal.

39 . A method, comprising:
providing a substrate comprising a substrate top side, a substrate bottom side, substrate lateral sides defining a perimeter of the substrate, a conductive structure at the perimeter of the substrate, and a mold material providing a portion of the substrate top side and a portion of the substrate bottom side; providing a semiconductor die coupled to the substrate top side; and providing an encapsulant that encapsulates the semiconductor die and contacts the mold material at the substrate top side; wherein the conductive structure comprises an upper portion and a lower portion adjoining the upper portion; wherein the upper portion of the conductive structure comprises an upper portion bottom side, an upper portion top side providing a portion of the substrate top side, and an upper portion lateral side exposed at the perimeter of the substrate; wherein the lower portion of the conductive structure comprises a lower portion bottom side providing a portion of the substrate bottom side and a lower portion lateral side exposed at the perimeter of the substrate; wherein the upper portion of the conductive structure is wider than the lower portion of the conductive structure; and wherein the mold material of the substrate contacts the upper portion bottom side.

40 . The method of claim 39 , comprising singulating along a singulation line to form a substrate lateral side of the substrate lateral sides, wherein the singulating includes singulating through the conductive structure of the substrate.

Assignees

• Amkor Tech Singapore Holding Pte Ltd

Inventors

• Bang Won Bae
• Oh Kwang Seok

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701 Primary

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title