Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems

Patent metadata

Field	Value
Publication number	US-2024349478-A1
Application number	US-202418619000-A
Country	US
Kind code	A1
Filing date	Mar 27, 2024
Priority date	Apr 14, 2023
Publication date	Oct 17, 2024
Grant date	—

Abstract

A method of forming a microelectronic device includes forming a first dielectric stack over a semiconductor base structure including pillar structures separated by filled isolation trenches. Digit line contacts are formed to partially vertically extend through the first dielectric stack and into digit line contact regions of the pillar structures. Digit lines are formed over and in contact with the digit line contacts, and partially vertically extend through the first dielectric stack. A second dielectric stack is formed over the digit lines and the first dielectric stack. Storage node contacts are formed to vertically extend partially through the second dielectric stack, completely through the first dielectric stack, and into storage node contact regions of the pillar structures. Redistribution layer structures are formed over and in contact with the storage node contacts, and partially vertically extend through the second dielectric stack. Microelectronic devices, memory devices, and electronic systems are also described.

First claim

What is claimed is:

1 . A method of forming a microelectronic device, comprising:
forming a first dielectric stack over a semiconductor base structure comprising pillar structures separated from one another by filled isolation trenches; forming digit line contacts partially vertically extending through the first dielectric stack and into digit line contact regions of the pillar structures; forming digit lines over and in contact with the digit line contacts, the digit lines partially vertically extending through the first dielectric stack; forming a second dielectric stack over the digit lines and the first dielectric stack; forming storage node contacts vertically extending partially through the second dielectric stack, completely through the first dielectric stack, and into storage node contact regions of the pillar structures; and forming redistribution layer (RDL) structures over and in contact with the storage node contacts, the RDL structures partially vertically extending through the second dielectric stack.

2 . The method of claim 1 , wherein forming a first dielectric stack comprises forming the first dielectric stack to comprise:
a first dielectric oxide material over the pillar structures and the filled isolation trenches; a first dielectric nitride material over the first dielectric oxide material; and a second dielectric oxide material over the first dielectric nitride material.

3 . The method of claim 1 , further comprising:
forming first sacrificial structures vertically extending completely through the first dielectric stack into digit line contact regions of the pillar structures; removing upper portions of the first sacrificial structures and the first dielectric stack to form digit line trenches horizontally extending through the first dielectric stack; removing remaining portions of the first sacrificial structures exposed by the digit line trenches to form digit line contact openings; forming the digit line contacts in the digit line contact openings; and forming the digit lines in the digit line trenches.

4 . The method of claim 3 , wherein forming first sacrificial structures comprises:
forming a first hardmask structure over the first dielectric stack, the first hardmask structure comprising:
a first underlayer (UL) material over the first dielectric stack;
a first developable anti-reflective coating (DARC) material over the first UL material;
a first resist adhesion layer (RAL) material over the first DARC material; and
a first extreme ultraviolet (EUV) resist material over the first RAL material;
forming first openings vertically extending completely through the first hardmask structure and the first dielectric stack and into the digit line contact regions of the pillar structures using a first material removal process employing EUV lithography; filling the first openings with first sacrificial material; and removing the first hardmask structure and upper portions of the first sacrificial material to form the first sacrificial structures.

5 . The method of claim 4 , wherein removing upper portions of the first sacrificial structures and the first dielectric stack comprises:
forming a second hardmask structure over the first sacrificial structures and the first dielectric stack, the second hardmask structure comprising:
a second UL material over the first sacrificial structures and the first dielectric stack;
a second DARC material over the second UL material;
a second RAL material over the second DARC material; and
a second EUV resist material over the second RAL material;
forming linear mask openings vertically extending completely through the second hardmask structure and to the first sacrificial structures and the first dielectric stack using a second material removal process employing additional EUV lithography; and extending a pattern of the linear mask openings within the second hardmask structure into the first dielectric stack and the first sacrificial structures to form the digit line trenches.

6 . The method of claim 5 , wherein forming the digit line contacts in the digit line contact openings comprises:
forming a first spacer material to partially fill the digit line contact openings and the digit line trenches; removing portions of the first spacer material at bottoms of the digit line contact openings to expose semiconductor material of the digit line contact regions of the pillar structures; growing epitaxial semiconductor material within lower portions of the digit line contact openings using the semiconductor material of the digit line contact regions of the pillar structures; forming metal silicide material over the epitaxial semiconductor material and within the digit line contact openings; and forming conductive material over the metal silicide material and substantially filling remaining portions of the digit line contact openings.

7 . The method of claim 6 , wherein forming the digit lines in the digit line trenches comprises:
forming an additional amount of the conductive material inside and outside of the digit line trenches, the additional amount of the conductive material substantially filling the digit line trenches; and removing a portion of the additional amount of the conductive material overlying upper boundaries of the first dielectric stack, remaining portions of the additional amount of the conductive material within the digit line trenches forming the digit lines.

8 . The method of claim 1 , wherein forming a second dielectric stack over the digit lines and the first dielectric stack comprises:
forming a first dielectric nitride material over the digit lines and the first dielectric stack using a first deposition process; and forming a second dielectric nitride material over the first dielectric nitride material using a second deposition process, the first deposition process employing relatively lower temperatures than the second deposition process.

9 . The method of claim 8 , wherein forming storage node contacts comprises:
forming storage node contact openings vertically completely through the second dielectric stack and the first dielectric stack and into storage node contact regions of the pillar structures; forming first dielectric spacer structures continuously vertically extending along horizontal boundaries of the storage node contact openings; growing epitaxial semiconductor material within the storage node contact openings and horizontally surrounded by the first dielectric spacer structures using semiconductor material of the storage node contact regions of the pillar structures; removing portions of the second dielectric nitride material and the epitaxial semiconductor material to form RDL openings, the RDL openings overlying the first dielectric nitride material; removing upper portions of the epitaxial semiconductor material within upper regions of the storage node contact openings after forming RDL openings; forming second dielectric spacer structures over remaining portions of the epitaxial semiconductor material and within the upper regions of the storage node contact openings; forming metal silicide material within the upper regions of the storage node contact openings and horizontally surrounded by the second dielectric spacer structures; and forming conductive material over the metal silicide material and substantially filling remainders of the upper regions of the storage node contact openings.

10 . The method of claim 9 , wherein forming RDL structures over and in contact with the storage node contacts comprises:
forming an additional amount of the conductive material inside and outside of the RDL openings, the additional amount of the conductive

Assignees

• Micron Technology Inc

Inventors

• Simsek-Ege Fatma Arzum
• Light Scott L
• Ege Efe S
• Yao Chunhua

Classifications

• H10B12/0335 Primary

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/485

  Bit line contacts · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10B12/482 Primary

  Bit lines · CPC title