Integrated circuit structures including a titanium silicide material

Patent metadata

Field	Value
Publication number	US-2024332392-A1
Application number	US-202418737616-A
Country	US
Kind code	A1
Filing date	Jun 7, 2024
Priority date	Jun 25, 2020
Publication date	Oct 3, 2024
Grant date	—

Abstract

Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi 2 .

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a nanowire; a gate electrode surrounding a channel region of the nanowire; a first epitaxial semiconductor source or drain structure at a first end of the channel region at a first side of the gate electrode, the first epitaxial semiconductor source or drain structure having a non-flat topography; a first dielectric spacer in contact with a side of the first epitaxial semiconductor source or drain structure; a second epitaxial semiconductor source or drain structure at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end, the second side opposite the first side, and the second epitaxial semiconductor source or drain structure having a non-flat topography; a second dielectric spacer in contact with a side of the second epitaxial semiconductor source or drain structure; a titanium silicide material in direct contact with each of the first and second epitaxial semiconductor source or drain structures and with each of the first and second dielectric spacers, the titanium silicide material conformal with and hermetically sealing the non-flat topography of each of the first and second epitaxial semiconductor source or drain structures, and the titanium silicide material having a total atomic composition comprising 95 % or greater stoichiometric TiSi 2 ; and a dielectric wall adjacent to the first dielectric spacer, wherein the first dielectric spacer is laterally between the dielectric wall and the first epitaxial semiconductor source or drain structure, and wherein the dielectric wall is in contact with the first dielectric spacer and in contact with the titanium silicide material.

2 . The integrated circuit structure of claim 1 , wherein the titanium silicide material has a total atomic composition comprising 98 % or greater of stoichiometric TiSi 2 .

3 . The integrated circuit structure of claim 1 , wherein the total atomic composition of titanium silicide material further comprises a non-zero amount but less than 1% of phosphorous, boron or germanium.

4 . The integrated circuit structure of claim 1 , wherein the titanium silicide material has a C 49 crystalline phase or a C 54 crystalline phase.

5 . The integrated circuit structure of claim 1 , wherein the titanium silicide material has a thickness variation of 10% or less along the non-flat topography of each of the first and second epitaxial semiconductor source or drain structures.

6 . The integrated circuit structure of claim 1 , wherein the non-flat topography of each of the first and second epitaxial semiconductor source or drain structures comprises a raised central portion and lower side portions.

7 . The integrated circuit structure of claim 1 , wherein the first epitaxial semiconductor source or drain structure and the second epitaxial semiconductor source or drain structure both comprise silicon.

8 . The integrated circuit structure of claim 7 , wherein the first epitaxial semiconductor source or drain structure and the second epitaxial semiconductor source or drain structure both further comprise germanium.

9 . The integrated circuit structure of claim 1 , further comprising:
a conductive fill material on the titanium silicide material.

10 . The integrated circuit structure of claim 1 , further comprising:
a second nanowire, wherein the gate electrode further surrounds a channel region of the second nanowire; a third epitaxial semiconductor source or drain structure at a first end of the channel region of the second nanowire at the first side of the gate electrode, the third epitaxial semiconductor source or drain structure having a non-flat topography; and a fourth epitaxial semiconductor source or drain structure at a second end of the channel region of the second nanowire at the second side of the gate electrode, the second end opposite the first end, the fourth epitaxial semiconductor source or drain structure having a non-flat topography, wherein the titanium silicide material is in direct contact with each of the third and fourth epitaxial semiconductor source or drain structures, the titanium silicide material conformal with and hermetically sealing the non-flat topography of each of the third and fourth epitaxial semiconductor source or drain structures, and the titanium silicide material continuous between the first and third epitaxial semiconductor source or drain structures and continuous between the second and fourth epitaxial semiconductor source or drain structures.

11 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a nanowire;
a gate electrode surrounding a channel region of the nanowire;
a first epitaxial semiconductor source or drain structure at a first end of the channel region at a first side of the gate electrode, the first epitaxial semiconductor source or drain structure having a non-flat topography;
a first dielectric spacer in contact with a side of the first epitaxial semiconductor source or drain structure;
a second epitaxial semiconductor source or drain structure at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end, the second side opposite the first side, the second epitaxial semiconductor source or drain structure having a non-flat topography;
a second dielectric spacer in contact with a side of the second epitaxial semiconductor source or drain structure; a titanium silicide material in direct contact with each of the first and second epitaxial semiconductor source or drain structures and with each of the first and second dielectric spacers, the titanium silicide material conformal with and hermetically sealing the non-flat topography of each of the first and second epitaxial semiconductor source or drain structures, and the titanium silicide material; and a dielectric wall adjacent to the first dielectric spacer, wherein the first dielectric spacer is laterally between the dielectric wall and the first epitaxial semiconductor source or drain structure, and wherein the dielectric wall is in contact with the first dielectric spacer and in contact with the titanium silicide material.

12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.

13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

14 . The computing device of claim 11 , further comprising:
a camera coupled to the board.

15 . The computing device of claim 11 , further comprising:
a battery coupled to the board.

16 . The computing device of claim 11 , further comprising:
an antenna coupled to the board.

17 . The computing device of claim 11 , further comprising:
a display coupled to the board.

18 . The computing device of claim 11 , wherein the titanium silicide material of the integrated circuit structure has a total atomic composition comprising 98 % or greater of stoichiometric TiSi 2 .

19 . The computing device of claim 11 , wherein the total atomic composition of titanium silicide material of the integrated circuit structure further comprises a non- zero amount but less than 1 % of phosphorous, boron or germanium.

20 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

Assignees

• Intel Corp

Inventors

• Lavric Dan S
• Glass Glenn A
• Troeger Thomas T
• Vishwanath Suresh
• Jha Jitendra Kumar
• Richards John F
• Murthy Anand S
• Mukherjee Srijit

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/151 Primary

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title