Polycrystalline silicon carbide substrate and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2024332011-A1
Application number	US-202418614538-A
Country	US
Kind code	A1
Filing date	Mar 22, 2024
Priority date	Mar 31, 2023
Publication date	Oct 3, 2024
Grant date	—

Abstract

At least one embodiment of a method of manufacturing includes forming a first polycrystalline silicon carbide (SiC) substrate with a sintering process by sintering one or more powdered semiconductor materials. After the first polycrystalline SiC substrate is formed utilizing the sintering process, the first polycrystalline silicon carbide SiC substrate is utilized to form a second polycrystalline SiC substrate with a chemical vapor deposition (CVD) process. The second polycrystalline SiC substrate is formed on a surface of the first polycrystalline SiC substrate by depositing SiC on the surface of the first polycrystalline SiC substrate with the CVD process. As the first and second polycrystalline SiC substrates are made of the same or similar semiconductor material (e.g., SiC), a first coefficient of thermal expansion (CTE) for the first polycrystalline SiC substrate is the same or similar to the second CTE of the second polycrystalline SiC substrate.

First claim

1 . A method, comprising:
forming a carrier polycrystalline silicon carbide (SiC) substrate having a surface, forming the carrier polycrystalline SiC substrate including:
sintering one or more powdered materials to form the carrier polycrystalline SiC substrate; and
forming a polycrystalline SiC substrate on the surface of the carrier polycrystalline SiC substrate, forming the polycrystalline SiC substrate including:
depositing SiC onto the surface of the carrier polycrystalline SiC substrate with a chemical vapor deposition (CVD) process.

2 . The method of claim 1 , further comprising cooling the polycrystalline SiC substrate and the carrier polycrystalline SiC substrate.

3 . The method of claim 1 , wherein the carrier polycrystalline SiC substrate has a first coefficient of thermal expansion (CTE) and the polycrystalline SiC substrate has a second CTE, and the first CTE is substantially equal to the second CTE.

4 . The method of claim 1 , further comprising polishing a surface of the polycrystalline SiC substrate facing away from the surface of the carrier polycrystalline SiC substrate to have a roughness less than or equal to 5 angstroms (Å).

5 . The method of claim 1 , further comprising removing the polycrystalline SiC substrate from the carrier polycrystalline SiC substrate.

6 . The method of claim 5 , wherein removing the polycrystalline SiC substrate from the carrier polycrystalline SiC substrate includes grinding away the carrier polycrystalline SiC substrate.

7 . The method of claim 6 , wherein grinding away the carrier polycrystalline SiC substrate further includes exposing a surface of the polycrystalline SiC substrate.

8 . The method of claim 6 , further comprising forming one or more semiconductor layers on a surface of the polycrystalline SiC substrate.

9 . The method of claim 8 , wherein the one or more semiconductor layers includes at least one monocrystalline layer.

10 . The method of claim 9 , wherein the at least one monocrystalline layer is a monocrystalline SiC layer.

11 . A device, comprising:
a first polycrystalline SiC substrate including a first surface and a second surface opposite to the first surface, the first polycrystalline SiC substrate having a first cubic structure; and a second polycrystalline SiC substrate coupled to the second surface of the first polycrystalline SiC substrate, the second polycrystalline SiC substrate has a second cubic structure.

12 . The device of claim 11 , wherein:
the first polycrystalline SiC substrate has a first sidewall; and the second polycrystalline SiC substrate has a second sidewall substantially coplanar with the first sidewall.

13 . The device of claim 11 , wherein:
the first polycrystalline SiC substrate has a first coefficient of thermal expansion (CTE); the second polycrystalline SiC substrate has a second CTE; and the first CTE is substantially equal to the second CTE.

14 . The device of claim 11 , wherein the second polycrystalline SiC substrate includes a third surface that faces away from the first surface.

15 . The device of claim 11 , wherein the second polycrystalline SiC substrate includes a third surface facing away from the first polycrystalline SiC substrate, and the third surface of the second polycrystalline SiC substrate has a roughness less than or equal to 5 angstroms (Å).

16 . A method, comprising:
forming a polycrystalline SiC substrate with a first coefficient of thermal expansion on a first surface of a polycrystalline SiC carrier substrate with a second coefficient of thermal expansion substantially equal to the first coefficient of thermal expansion, forming the polycrystalline SiC substrate includes forming a second surface of the polycrystalline SiC substrate facing away from the carrier polycrystalline SiC substrate; and after forming the polycrystalline SiC substrate, removing the polycrystalline SiC substrate from the carrier polycrystalline SiC substrate.

17 . The method of claim 16 , further comprising polishing the second surface of the polycrystalline SiC substrate to have a roughness less than or equal to 20 angstroms (Å).

18 . The method of claim 16 , further comprising forming a monocrystalline SiC layer on the second surface of the polycrystalline SiC substrate.

19 . The method of claim 18 , wherein the polycrystalline SiC substrate has a first density and the monocrystalline SiC layer has a second density substantially equal to the first density.

20 . The method of claim 16 , further comprising wherein the polycrystalline SiC substrate and the polycrystalline SiC carrier substrate have a cubic structure.

Assignees

• St Microelectronics Int Nv

Inventors

• Magnusson Lindgren Björn
• Ellison Alexandre
• Riva Carlo

Classifications

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P90/1904

  Preparing vertically inhomogeneous wafers · CPC title

• H10P56/00

  Debonding of wafers, substrates or parts of devices · CPC title

• H10P14/2904 Primary

  Silicon carbide · CPC title