Semiconductor storage device

Patent metadata

Field	Value
Publication number	US-2024315026-A1
Application number	US-202418599913-A
Country	US
Kind code	A1
Filing date	Mar 8, 2024
Priority date	Mar 14, 2023
Publication date	Sep 19, 2024
Grant date	—

Abstract

According to one embodiment, in a semiconductor storage device, a plurality of second pillars each includes a first sub-pillar that is a single substance of a first insulating layer extending in the stacking direction in a lower layer side of a stacked body and a second sub-pillar arranged at a height position in an upper layer side of the stacked body to correspond to the first sub-pillar. The second sub-pillar includes a semiconductor layer extending in the stacking direction at the height position in the upper layer side of the stacked body, a second insulating layer covering a sidewall of the semiconductor layer, a third insulating layer covering a sidewall of the second insulating layer, and a fourth insulating layer that includes a different material from the second and third insulating layers and is interposed between the second and third insulating layers.

First claim

What is claimed is:

1 . A semiconductor storage device comprising:
a stacked body including a plurality of conductive layers stacked apart from each other, the plurality of conductive layers being processed into a step shape in a stepped portion; a first pillar that extends in a stacking direction of the stacked body in the stacked body different from the stepped portion and forms a memory cell at each intersection portion with at least a part of the plurality of conductive layers; and a plurality of second pillars that extends in the stacking direction in the stepped portion, wherein the plurality of second pillars each includes: a first sub-pillar that is a single substance of a first insulating layer extending in the stacking direction in a lower layer side of the stacked body; and a second sub-pillar arranged at a height position in an upper layer side of the stacked body to correspond to the first sub-pillar, and the second sub-pillar includes: a semiconductor layer extending in the stacking direction at the height position in the upper layer side of the stacked body; a second insulating layer covering a sidewall of the semiconductor layer; a third insulating layer covering a sidewall of the second insulating layer; and a fourth insulating layer that includes a different material from the second and third insulating layers and is interposed between the second and third insulating layers.

2 . The semiconductor storage device according to claim 1 , further comprising:
a plurality of third pillars that extends in the stacking direction in the stepped portion at a position overlapping in the staking direction with a portion where upper-side conductive layers of the plurality of conductive layers are processed into a step shape, wherein the plurality of third pillars each includes: the semiconductor layer that extends in the stacking direction from the upper layer side to the lower layer side of the stacked body; the second insulating layer covering the sidewall of the semiconductor layer; the third insulating layer covering the sidewall of the second insulating layer; and the fourth insulating layer interposed between the second and third insulating layers.

3 . The semiconductor storage device according to claim 2 , further comprising:
a plurality of fourth pillars that extends in the stacking direction in the stepped portion at a position overlapping in the stacking direction with a portion where lower-side conductive layers of the plurality of conductive layers are processed into a step shape, wherein the plurality of fourth pillars each is a single substance of the first insulating layer having an upper end portion at a position corresponding to a bottom surface of the upper layer side of the stacked body, and the plurality of second pillars is arranged between the plurality of third pillars and the plurality of fourth pillars.

4 . The semiconductor storage device according to claim 3 , further comprising:
a plate-like portion that extends in the stacking direction and a first direction intersecting the stacking direction and divides the stacked body in a second direction intersecting both directions of the stacking direction and the first direction; and a plurality of fifth pillars arrayed in the first direction adjacently to the plate-like portion on both sides in the second direction of the plate-like portion at a position overlapping in the stacking direction with a portion where the upper-side conductive layers are processed into the step shape, wherein the plurality of fifth pillars each includes: a fifth insulating layer that extends in the stacking direction in the lower layer side and the upper layer side of the stacked body.

5 . The semiconductor storage device according to claim 4 , further comprising:
a separation layer that penetrates an uppermost conductive layer among the plurality of conductive layers or penetrates the uppermost conductive layer and at least one conductive layer of the plurality of conductive layers continuous with the uppermost conductive layer in the stacking direction, extends in the first direction, and selectively separates one or more conductive layers of the plurality of conductive layers including the uppermost conductive layer in the second direction, wherein the plurality of third pillars is distributed and arranged, including a position adjacent to the plate-like portion in a region overlapping in the stacking direction with a portion where the one or more conductive layers are processed into a step shape.

6 . The semiconductor storage device according to claim 5 , wherein
the plurality of fifth pillars is arranged adjacently to the plate-like portion on both sides in the second direction of the plate-like portion, such that an arrangement of the plurality of fifth pillars is local within a region overlapping in the stacking direction with the portion where the upper-side conductive layers are processed into the step shape among regions overlapping in the stacking direction with the portions where the upper-side and lower-side conductive layers are processed into the step shape respectively and the region overlapping in the stacking direction with the portion where the one or more conductive layers are processed into the step shape.

7 . The semiconductor storage device according to claim 2 , wherein
the plurality of second pillars is distributed and arranged in a region overlapping in the stacking direction with a portion where lower-side conductive layers of the plurality of conductive layers are processed into a step shape.

8 . The semiconductor storage device according to claim 7 , wherein
a maximum cross-sectional area of the first sub-pillar is larger than a maximum cross-sectional area of the second sub-pillar, as viewed from the stacking direction.

9 . The semiconductor storage device according to claim 7 , wherein
a pitch between first sub-pillars included in the plurality of second pillars is different from a pitch between second sub-pillars included in the plurality of second pillars in correspondence with the first sub-pillars, as viewed from the stacking direction.

10 . The semiconductor storage device according to claim 9 , wherein
the pitch between the second sub-pillars is larger than the pitch between the first sub-pillars.

11 . The semiconductor storage device according to claim 7 , further comprising:
a plate-like portion that extends in the stacking direction and a first direction intersecting the stacking direction and divides the stacked body in a second direction intersecting both directions of the stacking direction and the first direction; and a plurality of fifth pillars arrayed in the first direction adjacently to the plate-like portion on both sides in the second direction of the plate-like portion in the stepped portion, wherein the plurality of fifth pillars each includes: a fifth insulating layer that extends in the stacking direction in the lower layer side of the stacked body and at the height position in the upper layer side of the stacked body.

12 . The semiconductor storage device according to claim 11 , further comprising:
a separation layer that penetrates an uppermost conductive layer among the plurality of conductive layers or penetrates the uppermost conductive layer and at least one conductive layer of the plurality of conductive layers continuous with the uppermost conductive layer in the stacking direction, extends in the first direction, and selectively separates one or more conductive layers of the plurality of conductive layers including the uppermost conductive layer in the second direction, where

Assignees

• Kioxia Corp

Inventors

• Watarai ayumi
• Tashiro Kenji
• Noda Kosei

Classifications

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title