Low power management for sleep mode operation of a memory device

Patent metadata

Field	Value
Publication number	US-2024312494-A1
Application number	US-202418675997-A
Country	US
Kind code	A1
Filing date	May 28, 2024
Priority date	Dec 22, 2020
Publication date	Sep 19, 2024
Grant date	—

Abstract

In a memory sub-system, causing a standby circuit associated with a memory device to enter into a low power mode. In the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device, where the standby current level is lower than a current level supplied when the memory device is in an active mode.

First claim

What is claimed is:

1 . A memory sub-system comprising:
a standby circuit comprising a voltage regulator operatively coupled to a memory device; and control logic, operatively coupled to the standby circuit, to perform operations comprising:
causing the standby circuit associated with the memory device to enter into a low power mode; and
in the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device, wherein the standby current level is lower than a current level supplied when the memory device is in an active mode.

2 . The memory sub-system of claim 1 , wherein the memory device is maintained in a powered state during the low power mode.

3 . The memory sub-system of claim 1 , wherein the memory device is in a sleep mode during supply of the standby current level.

4 . The memory sub-system of claim 1 , wherein the voltage regulator generates an output voltage that is limited based on the reference voltage.

5 . The memory sub-system of claim 1 , wherein the standby current level is limited based on the reference voltage.

6 . The memory sub-system of claim 1 , the operations further comprising:
in the low power mode, disabling supplying an output of a bandgap circuit of the standby circuit to the voltage regulator.

7 . The memory sub-system of claim 1 , the operations further comprising initiating an exit from the low power mode to transition the memory device from a sleep mode to the active mode.

8 . A memory device comprising:
an array of memory cells coupled to a first circuit comprising a voltage regulator; and control logic, operatively coupled with the first circuit, to perform operations comprising:
causing the first circuit to enter into a low power mode; and
in the low power mode, causing a reference voltage to be supplied to the voltage regulator, wherein the reference voltage causes the voltage regulator to supply a first current level to the memory device, wherein the first current level is lower than a current level supplied when the memory device is in an active mode.

9 . The memory device of claim 8 , wherein the memory device is maintained in a powered state during the low power mode.

10 . The memory device of claim 8 , wherein the memory device is in a sleep mode during supply of the first current level.

11 . The memory device of claim 8 , wherein the voltage regulator generates an output voltage that is limited based on the reference voltage.

12 . The memory device of claim 8 , wherein the first current level is limited based on the reference voltage.

13 . The memory device of claim 8 , the operations further comprising:
in the low power mode, disabling supplying an output of a bandgap circuit of the first circuit to the voltage regulator.

14 . The memory device of claim 8 , the operations further comprising initiating an exit from the low power mode to transition the memory device from a sleep mode to the active mode.

15 . A method comprising:
causing, by a processing device of a memory sub-system, a standby circuit associated with a memory device to enter into a low power mode; and in the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device, wherein the standby current level is lower than a current level supplied when the memory device is in an active mode.

16 . The method of claim 15 , wherein the voltage regulator generates an output voltage that is limited based on the reference voltage.

17 . The method of claim 15 , further comprising maintaining the memory device in a powered state during the low power mode.

18 . The method of claim 15 , wherein the memory device is in a sleep mode during supply of the standby current level.

19 . The method of claim 15 , wherein the first voltage level is limited based on the reference voltage.

20 . The method of claim 15 , further comprising in the low power mode, disabling supplying an output of a bandgap circuit of the standby circuit to the voltage regulator.

Assignees

• Micron Technology Inc

Inventors

• Xu Shuai
• Piccardi Michele
• Muralidharan Arvind
• Lee June
• Lin Qisong
• Stoller Scott A
• Shen Jun

Classifications

• G11C11/1697

  Power supply circuits · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C11/2297

  Power supply circuits · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title