Low power management for sleep mode operation of a memory device

Patent metadata

Field	Value
Publication number	US-12027227-B2
Application number	US-202017426963-A
Country	US
Kind code	B2
Filing date	Dec 22, 2020
Priority date	Dec 22, 2020
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.

First claim

What is claimed is:

1. A method comprising:
determining, by a processing device of a controller of a memory sub-system, that a memory device of a memory sub-system is to be transitioned from an active mode to a sleep mode;
initiating a command to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state; and
in the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device during the sleep mode, wherein the standby current level is lower than a current level supplied when the memory device is in the active mode.

2. The method of claim 1 , wherein the voltage regulator generates an output voltage that is limited based on the reference voltage.

3. The method of claim 1 , wherein the standby current level is limited based on the reference voltage.

4. The method of claim 1 , further comprising:
in the low power mode, disabling supplying an output of a bandgap circuit of the standby circuit to the voltage regulator.

5. The method of claim 1 , further comprising initiating an exit from the low power mode to transition the memory device from the sleep mode to an active mode.

6. The method of claim 5 , wherein the power supply is in the powered state during transition of the memory device from the sleep mode to the active mode.

7. The method of claim 1 , wherein determining the memory device is to be transitioned to the sleep mode further comprises:
determining a workload queue associated with the memory device is empty; and
determining the memory device is in an idle mode.

8. A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:
determining that a memory device of a memory sub-system is to be transitioned from an active mode to a sleep mode;
initiating a command to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state; and
in the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device during the sleep mode, wherein the standby current level is lower than a current level supplied when the memory device is in the active mode.

9. The non-transitory computer readable medium of claim 8 , wherein a first power supply of the memory sub-system is powered on during operation the sleep mode.

10. The non-transitory computer readable medium of claim 9 , wherein the memory sub-system further comprises a second power supply that is powered on during operation in the sleep mode.

11. The non-transitory computer readable medium of claim 9 , wherein the memory sub-system further comprises a second power supply, and wherein the low power mode is entered following a powering down of the second power supply.

12. The non-transitory computer readable medium of claim 11 , wherein the low power mode is exited following a powering up of the second power supply.

13. The non-transitory computer readable medium of claim 8 , the operations further comprising in the low power mode, disabling supplying an output of a bandgap circuit of the standby circuit to the voltage regulator.

14. A memory sub-system comprising:
a memory device comprising a standby circuit comprising a voltage regulator operatively coupled to one or more memory cells of the memory device; and
control logic, operatively coupled with the standby circuit, to perform operations comprising:
determining that the memory device is to be transitioned from an active mode to a sleep mode;
initiating a command to cause the standby circuit to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state; and
in the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device during the sleep mode, wherein the standby current level is lower than a current level supplied when the memory device is in the active mode.

15. The memory sub-system of claim 14 , wherein the voltage regulator generates an output voltage that is limited based on the reference voltage.

16. The memory sub-system of claim 14 , wherein the standby current level is limited based on the reference voltage.

17. The memory sub-system of claim 14 , the operations further comprising, in the low power mode, disabling supplying an output of a bandgap circuit of the standby circuit to the voltage regulator.

18. The memory sub-system of claim 14 , the operations further comprising initiating an exit from the low power mode to transition the memory device from the sleep mode to the active mode.

19. The memory sub-system of claim 18 , wherein the power supply is in the powered state during the transition of the memory device from the sleep mode to the active mode.

20. The memory sub-system of claim 14 , wherein determining the memory device is to be transitioned to the sleep mode further comprises:
determining a workload queue associated with the memory device is empty; and

determining the memory device is in an idle mode.

Assignees

• Micron Technology Inc

Inventors

• Xu Shuai
• Piccardi Michele
• Muralidharan Arvind
• Lee June
• Lin Qisong
• Stoller Scott A
• Shen Jun

Classifications

• G11C11/1697

  Power supply circuits · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C11/2297

  Power supply circuits · CPC title

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title