Power Semiconductor Package

Patent metadata

Field	Value
Publication number	US-2024304507-A1
Application number	US-202318179036-A
Country	US
Kind code	A1
Filing date	Mar 6, 2023
Priority date	Mar 6, 2023
Publication date	Sep 12, 2024
Grant date	—

Abstract

Power semiconductor packages are provided. In one example, a power semiconductor package may include a power semiconductor die. The power semiconductor package may include a housing having a first side and a second side opposing the first side. The power semiconductor package may include one or more electrical leads extending from the first side. The power semiconductor package may include one or more leadless surface mount type (SMT) connection structures on the second side.

First claim

1 . A power semiconductor package, comprising:
a semiconductor die; a housing having a first side and a second side opposing the first side; one or more electrical leads extending from the first side; and one or more leadless surface mount type (SMT) connection structures on the second side.

2 . The power semiconductor package of claim 1 , wherein the one or more leadless SMT connection structures each comprise a wettable flank connection structure.

3 . The power semiconductor package of claim 2 , wherein the wettable flank connection structure is partially encapsulated by the housing such that a connection surface of the wettable flank connection structure is exposed through a mounting surface of the housing.

4 . The power semiconductor package of claim 3 , wherein the wettable flank connection structure is exposed through at least one side surface of the housing.

5 . The power semiconductor package of claim 1 , wherein each of the one or more leadless SMT connection structures has a larger connection surface relative to each of the one or more electrical leads.

6 . The power semiconductor package of claim 1 , wherein the power semiconductor package has a greater number of electrical leads on the first side relative to a number of leadless SMT connection structures on the second side.

7 . The power semiconductor package of claim 1 , wherein the one or more electrical leads comprise a first lead and a second lead, wherein the first lead has a size that is greater than a size of the second lead.

8 . The power semiconductor package of claim 1 , wherein the housing comprises a first surface defined between the first side and the second side and a second surface opposing the first surface, wherein the first surface comprises at least one creepage extension structure, the at least one creepage extension structure comprising a step structure.

9 . The power semiconductor package of claim 8 , wherein the at least one creepage extension structure comprises a first step structure between a thermal pad and the first side of the housing and a second step structure between the thermal pad and the second side of the housing.

10 . The power semiconductor package of claim 8 , wherein the step structure has a depth of about 0.5 mm to about 2.0 mm.

11 . The power semiconductor package of claim 8 , wherein the at least one creepage extension structure comprises a trench defined between the step structure and the one or more electrical leads.

12 . The power semiconductor package of claim 1 , further comprising a thermal pad that is electrically isolated from the one or more leadless SMT connection structures.

13 . The power semiconductor package of claim 12 , wherein the thermal pad is on an insulating layer of a mounting substrate for the semiconductor die.

14 . (canceled)

15 . The power semiconductor package of claim 1 , wherein the semiconductor die comprises a metal-oxide-semiconductor field-effect-transistor (MOSFET), wherein a first lead of the one or more electrical leads is connected to a gate of the MOSFET and a second lead of the one or more electrical leads is connected to a source of the MOSFET, wherein the one or more leadless SMT connection structures are connected to a drain of the MOSFET.

16 . (canceled)

17 . The power semiconductor package of claim 15 , wherein a third lead of the one or more electrical leads is connected to a source-kelvin contact of the MOSFET or a sensor contact of the MOSFET.

18 . The power semiconductor package of claim 15 , wherein the MOSFET comprises a silicon carbide-based MOSFET.

19 . The power semiconductor package of claim 1 , wherein the semiconductor die comprises a Schottky diode, wherein the one or more electrical leads are coupled to a first contact for the Schottky diode and the one or more SMT connection structures are coupled to a second contact for the Schottky diode.

20 . (canceled)

21 . The power semiconductor package of claim 19 , wherein the Schottky diode is a silicon carbide-based Schottky diode.

22 . A power semiconductor package, comprising:
a semiconductor die; a housing having a first side and a second side opposing the first side; one or more electrical leads extending from the first side; one or more surface mount type (SMT) connection structures on the second side; and wherein each of the one or more SMT connection structures has a connection surface area that is greater than a connection surface area of each of the one or more electrical leads.

23 .- 31 . (canceled)

32 . A power semiconductor package, comprising:
a semiconductor die; a housing having a first side and a second side opposing the first side, the housing having a first surface extending between the first side and the second side and a second surface opposing the first surface; a thermal pad on the first surface; and a step structure on the first surface of the housing, the step structure defined in the housing such that a first portion of the housing at the first side has a first thickness and a second portion of the housing at the thermal pad has a second thickness, the second thickness being greater than the first thickness.

33 .- 69 . (canceled)

Assignees

• Wolfspeed Inc

Inventors

• Dezsi Geza
• Lin Yusheng
• Saxena Kuldeep

Classifications

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/481 Primary

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/429

  being the outer leads · CPC title