String driver connections for wafer on wafer packaging

Patent metadata

Field	Value
Publication number	US-2024274533-A1
Application number	US-202418416227-A
Country	US
Kind code	A1
Filing date	Jan 18, 2024
Priority date	Feb 15, 2023
Publication date	Aug 15, 2024
Grant date	—

Abstract

A semiconductor device assembly including a first wafer having complementary metal-oxide-semiconductor (CMOS) devices, the CMOS devices including a plurality of string drivers, wherein each of the plurality of string drivers includes a field effect transistor (FET), a global word line connected to a source of the FET, and a local word line vertically passing through the FET; and a second wafer having a memory array including a plurality of word lines, each of the word lines being connected to a corresponding one of the string drivers of the first wafer through a local word line of the corresponding string driver, wherein a backside surface of the first wafer is bonded to a frontside surface of the second wafer to form a wafer-on-wafer (WOW) bonding.

First claim

What is claimed is:

1 . A semiconductor device assembly, comprising:
a first wafer having complementary metal-oxide-semiconductor (CMOS) devices, the CMOS devices including a plurality of string drivers, wherein each of the plurality of string drivers includes a field effect transistor (FET), a global word line connected to a source of the FET, and a local word line vertically passing through the FET; and a second wafer having a memory array including a plurality of word lines, each of the word lines being connected to a corresponding one of the string drivers of the first wafer through a local word line of the corresponding string driver; wherein a backside surface of the first wafer is bonded to a frontside surface of the second wafer to form a wafer-on-wafer (WOW) bonding.

2 . The semiconductor device assembly of claim 1 , wherein the FET of each of the plurality of string drivers of the first wafer is a metal-oxide-semiconductor FET (MOSFET) including a gate, a source, and a drain.

3 . The semiconductor device assembly of claim 2 , wherein the global word line of each of the plurality of string drivers is connected to the source of the MOSFET, and wherein the local word line of each of the plurality of string drivers vertically passes through at least a portion of the drain of the MOSFET.

4 . The semiconductor device assembly of claim 3 , wherein the drain of the MOSFET of each of the plurality of string drivers includes a lightly doped drain region and a heavily doped drain region, both of which vertically extend through a substrate of the MOSFET, wherein the lightly doped drain region is disposed between the gate of the MOSFET and the heavily doped drain region of the MOSFET.

5 . The semiconductor device assembly of claim 4 , wherein the local word line of each of the plurality of string drivers vertically passes through the heavily doped drain region of corresponding MOSFET.

6 . The semiconductor device assembly of claim 4 , wherein the first wafer includes a plurality of local deep trench (LDT) regions comprising dielectric materials, each of the plurality of LDT regions being disposed adjacent to the heavily doped drain region of corresponding one of the plurality of string drivers.

7 . The semiconductor device assembly of claim 6 , wherein the local word line of each of the plurality of string drivers vertically passes through the heavily doped drain region and adjacent LDT region of corresponding one of the plurality of string drivers.

8 . The semiconductor device assembly of claim 2 , wherein the source of the MOSFET of each of the plurality of string drivers includes a lightly doped source region and a heavily doped source region, the heavily doped source region being embedded in the lightly doped source region, and wherein the global word line of each of the plurality of string drivers is connected to the heavily doped source region of the corresponding string driver.

9 . The semiconductor device assembly of claim 1 , wherein the first wafer comprise a dielectric layer disposed at the backside surface of the first wafer and below the plurality of string drivers, and wherein the dielectric layer of the first wafer is bonded to a dielectric layer disposed at the frontside surface of the second wafer to form the WOW bonding.

10 . The semiconductor device assembly of claim 1 , wherein the local word line of each of the plurality of string drivers vertically passes through the first wafer including the corresponding FET of the string driver and the dielectric layer of the first wafer, and wherein the local word line of each of the plurality of string drivers is further extended into the second wafer through the WOW bonding interface and is connected to a metal pad, the metal pad being connected to a corresponding word line of the memory array of the second wafer.

11 . A semiconductor device, comprising:
a gate disposed at least on a top surface of a substrate; a source disposed at one end of the gate and in the substrate, the source having a lightly doped source region and a heavily doped source region, wherein the heavily doped source region is embedded in the lightly doped source region; a drain disposed at another end of the gate and in the substrate, the drain having a lightly doped drain region and a heavily doped drain region, both of which vertically extend through a substrate of the semiconductor device; wherein the lightly doped drain region is disposed between the gate and the heavily doped drain region.

12 . The semiconductor device of claim 11 , further comprising:
a global word line that is connected to the heavily doped source region of the semiconductor device; and a local word line that vertically passes through the drain of the semiconductor device.

13 . The semiconductor device of claim 12 , wherein the local word line vertically passes through the heavily doped drain of the semiconductor device.

14 . The semiconductor device of claim 12 , further comprising a local deep trench (LDT) region comprising dielectric materials, the LDT region being disposed adjacent to the heavily doped drain region of the semiconductor device, wherein the local word line vertically passes through the heavily doped drain region and adjacent LDT region of the semiconductor device.

15 . The semiconductor device of claim 14 , further comprising a shallow trench isolation (STI) region comprising dielectric materials, the STI region being adjacent to and in parallel to the gate of the semiconductor device, wherein the STI region has a depth less than the LDT region.

16 . A method of forming a semiconductor device assembly, comprising:
providing a first wafer having complementary metal-oxide-semiconductor (CMOS) devices, the CMOS devices including a plurality of string drivers, wherein each of the plurality of string drivers includes a field effect transistor (FET); forming a plurality of global word line each being connected to a corresponding FET of one of the plurality of string drivers; thinning the first wafer from a backside surface of the first wafer; providing a second wafer having a memory array including a plurality of word lines; and bonding the backside surface of the first wafer to a frontside surface of the second wafer to form a wafer-on-wafer (WOW) bonding.

17 . The method of forming a semiconductor device assembly of claim 16 , wherein providing the first wafer comprises:
forming a gate at least on a top surface of a substrate of each of the plurality of string drivers; forming a source at one end of the gate and in the substrate, the source having a lightly doped source region and a heavily doped source region, wherein the heavily doped source region is embedded in the lightly doped source region; and forming a drain disposed at another end of the gate and in the substrate, the drain having a lightly doped drain region and a heavily doped drain region, both of which vertically extend through a substrate of the semiconductor device, wherein the lightly doped drain region is disposed between the gate and the heavily doped drain region.

18 . The method of forming a semiconductor device assembly of claim 17 , wherein providing the first wafer further comprises:
forming a local deep trench (LDT) region comprising dielectric materials in the substrate of each of the plurality of string drivers, the LDT region being disposed adjacent to the heavily doped drain region of the semiconductor device; and forming a shallow trench isolation (STI) region comprising dielectric materials in the substrate of

Assignees

• Micron Technology Inc

Inventors

• Smith Michael A
• Popp Martin W
• Hill Richard J

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title