Imaging element and semiconductor element

Patent metadata

Field	Value
Publication number	US-2024266381-A1
Application number	US-202418635309-A
Country	US
Kind code	A1
Filing date	Apr 15, 2024
Priority date	Mar 15, 2019
Publication date	Aug 8, 2024
Grant date	—

Abstract

An imaging element according to an embodiment of the present disclosure includes a first semiconductor substrate, and a second semiconductor substrate stacked over the first semiconductor substrate with an insulating layer interposed therebetween. The first semiconductor substrate includes a photoelectric conversion section, and a charge-holding section that holds charges transferred from the photoelectric conversion section. The second semiconductor substrate includes an amplification transistor that generates a signal of a voltage corresponding to a level of charges held in the charge-holding section. The amplification transistor includes a channel region, a source region, and a drain region in a plane intersecting a front surface of the second semiconductor substrate, and includes a gate electrode being opposed to the channel region with a gate insulating film interposed therebetween and being electrically coupled to the charge-holding section.

First claim

What is claimed is:

1 . An imaging element, comprising:
a first semiconductor substrate including a photoelectric conversion section and a charge-holding section that holds charges transferred from the photoelectric conversion section; and a second semiconductor substrate stacked over the first semiconductor substrate with an insulating layer interposed therebetween, the second semiconductor substrate including an amplification transistor that generates a signal of a voltage corresponding to a level of charges held in the charge-holding section, the amplification transistor including a channel region, a source region, and a drain region in a plane intersecting a front surface of the second semiconductor substrate, and including a gate electrode being opposed to the channel region with a gate insulating film interposed therebetween and being electrically coupled to the charge-holding section.

2 . The imaging element according to claim 1 , wherein the gate electrode has a double-gate structure sandwiching the channel region from a first direction parallel to the front surface of the second semiconductor substrate.

3 . The imaging element according to claim 1 , wherein the gate electrode has a tri-gate structure sandwiching the channel region from a first direction parallel to the front surface of the second semiconductor substrate and being opposed to the channel region with the gate insulating film interposed therebetween in a second direction intersecting the front surface of the second semiconductor substrate.

4 . The imaging element according to claim 1 , wherein the amplification transistor comprises a junctionless transistor in which the channel region, the source region, and the drain region have same polarity.

5 . The imaging element according to claim 1 , wherein
the amplification transistor includes a plurality of sets of the channel regions, the source regions, and the drain regions which are arranged side by side in the first direction, and the gate electrode is disposed to be opposed to each of the channel regions with the gate insulating film interposed therebetween in the amplification transistor.

6 . The imaging element according to claim 1 , wherein the gate electrode is formed by impurity-doped polysilicon, silicided silicon, or a metal material that controls a work function.

7 . The imaging element according to claim 2 , wherein
the first semiconductor substrate includes an element separation section that separates a plurality of the photoelectric conversion sections for the respective photoelectric conversion sections, and the amplification transistor is formed at a position opposed to the element separation section.

8 . The imaging element according to claim 7 , wherein
a plurality of the charge-holding sections are equally divided into a plurality of groups, a plurality of the amplification transistors are equally divided for the respective groups, the gate electrode includes a first partial electrode and a second partial electrode that sandwich the channel region from the first direction, and the plurality of the charge-holding sections are electrically coupled to corresponding ones of the amplification transistors in the respective groups by being linked to a lower end of one of the first partial electrode and the second partial electrode directly or via a coupling section.

9 . The imaging element according to claim 7 , wherein
a plurality of the charge-holding sections are equally divided into a plurality of groups, a plurality of the amplification transistors are equally divided for the respective groups, the imaging element further comprises a plurality of coupling pads assigned for the respective groups, and the plurality of the charge-holding sections are electrically coupled to corresponding ones of the amplification transistors via the coupling pads in the respective groups.

10 . The imaging element according to claim 7 , wherein
a plurality of the photoelectric conversion sections adjacent to each other among the plurality of the photoelectric conversion sections share the charge-holding section, a plurality of the amplification transistors are equally divided for each charge-holding section shared by the plurality of the photoelectric conversion sections, and the gate electrode is electrically coupled to the charge-holding section shared by the plurality of the photoelectric conversion sections.

11 . The imaging element according to claim 3 , wherein
the first semiconductor substrate includes an element separation section that separates a plurality of the photoelectric conversion sections for the respective photoelectric conversion sections, and the amplification transistor is formed at a position opposed to the element separation section.

12 . The imaging element according to claim 11 , wherein
a plurality of the charge-holding sections are equally divided into a plurality of groups, a plurality of the amplification transistors are equally divided for the respective groups, the gate electrode includes a first partial electrode and a second partial electrode that sandwich the channel region from the first direction, and a third partial electrode being opposed to the channel region with the gate insulating film interposed therebetween in the second direction and being in contact with the first partial electrode and the second partial electrode, and the plurality of the charge-holding sections are electrically coupled to corresponding ones of the amplification transistors in the respective groups by being linked to a lower end of one of the first partial electrode and the second partial electrode directly or via a coupling section.

13 . The imaging element according to claim 11 , wherein
a plurality of the charge-holding sections are equally divided into a plurality of groups, a plurality of the amplification transistors are equally divided for the respective groups, the imaging element further comprises a plurality of coupling pads assigned for the respective groups, and the plurality of the charge-holding sections are electrically coupled to corresponding ones of the amplification transistors via the coupling pads in the respective groups.

14 . The imaging element according to claim 11 , wherein
a plurality of the photoelectric conversion sections adjacent to each other among the plurality of the photoelectric conversion sections share the charge-holding section, a plurality of the amplification transistors are equally divided for each charge-holding section shared by the plurality of the photoelectric conversion sections, and the gate electrode is electrically coupled to the charge-holding section shared by the plurality of the photoelectric conversion sections.

15 . A semiconductor element, comprising:
a first semiconductor substrate including a first transistor or a photoelectric conversion section; and a second semiconductor substrate stacked over the first semiconductor substrate with an insulating layer interposed therebetween, the second semiconductor substrate including a second transistor, the second transistor including a channel region, a source region, and a drain region in a plane intersecting a front surface of the second semiconductor substrate, and including a gate electrode being opposed to the channel region with a gate insulating film interposed therebetween and being electrically coupled to the first semiconductor substrate.

16 . The semiconductor element according to claim 15 , wherein the gate electrode has a double-gate structure sandwiching the channel region from

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Miyake Shinichi
• Yamashita Hirofumi

Classifications

• H10F39/014

  of CMOS image sensors · CPC title

• H10F39/80373 Primary

  characterised by the gate of the transistor · CPC title

• H10F39/813 Primary

  Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels · CPC title

• H10F39/8023

  Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery · CPC title

• H10F39/811

  Interconnections · CPC title