Solid-state imaging element, sensor apparatus, and electronic device

US2019123079A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2019123079-A1
Application numberUS-201716086697-A
CountryUS
Kind codeA1
Filing dateMar 17, 2017
Priority dateMar 31, 2016
Publication dateApr 25, 2019
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to a solid-state imaging element, a sensor apparatus, and an electronic device capable of achieving better characteristics. A transistor constituting a pixel includes: a gate electrode having at least two fin portions formed so as to be buried from a planar portion planarly formed on a surface of a semiconductor substrate toward an inside of the semiconductor substrate; and a channel portion provided across a source and a drain so as to be in contact with side surfaces of the fin portions via an insulating film. In addition, a width of the channel portion is formed to be narrower than a depth of the fin portion. The present technology is applicable to a CMOS image sensor, for example.

First claim

Opening claim text (preview).

What is claimed is: 1 . A solid-state imaging element including a pixel having a transistor comprising: a gate electrode having at least one fin portion formed so as to be buried from a planar portion planarly formed on a surface of a semiconductor substrate toward an inside of the semiconductor substrate; and a channel portion provided across a source and a drain so as to be in contact with a side surface of the fin portion via an insulating film, the transistor being formed to have a width of the channel portion narrower than a depth of the fin portion. 2 . The solid-state imaging element according to claim 1 , wherein the gate electrode includes at least two fin portions, and the channel portion is formed in a region sandwiched between the fin portions. 3 . The solid-state imaging element according to claim 2 , wherein the channel portion is formed to allow both side surfaces to be in contact with the fin portion via the insulating film and allow a bottom surface side alone to be in contact with the semiconductor substrate. 4 . The solid-state imaging element according to claim 1 , further comprising a shallow trench isolation provided to surround the transistor and isolating the transistor from an outside. 5 . The solid-state imaging element according to claim 4 , wherein the shallow trench isolation is formed to be in contact with an outer side surface of the fin portion. 6 . The solid-state imaging element according to claim 4 , wherein a low concentration region having impurity concentration lower than in the channel portion is provided in the semiconductor substrate between the shallow trench isolation and the outer side surface of the fin portion. 7 . The solid-state imaging element according to claim 1 , wherein the gate electrode includes one fin portion, and the channel portion is provided between the fin portion and a shallow trench isolation provided to surround the transistor and isolating the transistor from an outside. 8 . The solid-state imaging element according to claim 1 , wherein a low concentration region having lower impurity concentration than in the channel portion is provided in the semiconductor substrate on a tip side of the fin portion. 9 . The solid-state imaging element according to claim 1 , wherein the transistor is an amplification transistor that amplifies an electric charge generated in a photoelectric conversion unit of the pixel and outputs the electric charge as a pixel signal. 10 . The solid-state imaging element according to claim 1 , wherein the transistor is a reset transistor that resets an electric charge in a floating diffusion region that temporarily accumulates an electric charge generated in the photoelectric conversion unit of the pixel. 11 . The solid-state imaging element according to claim 1 , wherein the transistor is a select transistor that connects the pixel and a signal line that outputs a pixel signal from the pixel. 12 . The solid-state imaging element according to claim 1 , wherein the transistor is a transfer transistor that transfers an electric charge generated in a photoelectric conversion unit of the pixel. 13 . The solid-state imaging element according to claim 12 , wherein the fin portion of the transfer transistor is formed to a depth reaching the photoelectric conversion unit formed at a deep position separate away from a substrate surface of the semiconductor substrate. 14 . A sensor apparatus including a sensor portion having a transistor comprising: a gate electrode having at least one fin portion formed so as to be buried from a planar portion planarly formed on a surface of a semiconductor substrate toward an inside of the semiconductor substrate; and a channel portion provided across a source and a drain so as to be in contact with a side surface of the fin portion via an insulating film, the transistor being formed to have a width of the channel portion narrower than a depth of the fin portion. 15 . An electronic device including a solid-state imaging element having a pixel having a transistor comprising: a gate electrode having at least one fin portion formed so as to be buried from a planar portion planarly formed on a surface of a semiconductor substrate toward an inside of the semiconductor substrate; and a channel portion provided across a source and a drain so as to be in contact with a side surface of the fin portion via an insulating film, the transistor being formed to have a width of the channel portion narrower than a depth of the fin portion.

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What does patent US2019123079A1 cover?
The present disclosure relates to a solid-state imaging element, a sensor apparatus, and an electronic device capable of achieving better characteristics. A transistor constituting a pixel includes: a gate electrode having at least two fin portions formed so as to be buried from a planar portion planarly formed on a surface of a semiconductor substrate toward an inside of the semiconductor subs…
Who is the assignee on this patent?
Sony Corp
What technology area does this patent fall under?
Primary CPC classification H01L27/14616. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Apr 25 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).