Semiconductor device

Patent metadata

Field	Value
Publication number	US-2024258186-A1
Application number	US-202418630486-A
Country	US
Kind code	A1
Filing date	Apr 9, 2024
Priority date	Dec 1, 2021
Publication date	Aug 1, 2024
Grant date	—

Abstract

A semiconductor device includes a semiconductor element, a conductor, and a sealing resin. The conductor includes a die pad, a first terminal, and a second terminal. The sealing resin covers a portion of the conductor and the semiconductor element. The sealing resin includes first, second, third and fourth resin surfaces. The die pad includes a first-lead obverse surface with the semiconductor element mounted, and a first-lead reverse surface exposed from the second resin surface. The first terminal is bent in a first sense of z direction and exposed from the third resin surface. The second terminal is bent in the first sense of z direction and exposed from the fourth resin surface. The first resin surface includes a recessed region recessed in z direction toward the second resin surface. As viewed in z direction, the recessed region overlaps with an imaginary line connecting the first terminal and the second terminal.

First claim

1 . A semiconductor device comprising:
a semiconductor element; a conductive member including a die pad portion, a first terminal portion, and a second terminal portion; and a sealing resin covering a portion of the conductive member and the semiconductor element, wherein the sealing resin includes a first resin surface facing in a first sense of a thickness direction of the sealing resin, a second resin surface facing in a second sense of the thickness direction, a third resin surface facing in a first sense of a first direction perpendicular to the thickness direction, and a fourth resin surface facing in a second sense of the first direction, the die pad portion includes: a mounting surface facing in the first sense of the thickness direction and on which the semiconductor element is mounted; and an exposed surface facing in the second sense of the thickness direction and exposed from the second resin surface, the first terminal portion is bent toward a side in the first sense of the thickness direction and exposed from the third resin surface, the second terminal portion is bent toward the side in the first sense of the thickness direction and exposed from the fourth resin surface, the first resin surface includes a recessed region recessed in the thickness direction toward the second resin surface, and the recessed region overlaps with an imaginary line connecting the first terminal portion and the second terminal portion as viewed in the thickness direction.

2 . The semiconductor device according to claim 1 , wherein the sealing resin includes a fifth resin surface facing in a first sense of a second direction perpendicular to the thickness direction and the first direction, and a sixth resin surface facing in a second sense of the second direction, and
the recessed region extends from the fifth resin surface to the sixth resin surface as viewed in the thickness direction.

3 . The semiconductor device according to claim 2 , wherein the recessed region includes: a valley that linearly extends from the fifth resin surface to the sixth resin surface as viewed in the thickness direction; and a first slope that meets the valley from a side in the first sense of the first direction and is inclined relative to the second resin surface, and
the first slope is inclined such that a depth of the recessed region increases with approach toward the valley.

4 . The semiconductor device according to claim 3 , wherein the recessed region includes a second slope that meets the valley from a side in the second sense of the first direction and is inclined relative to the second resin surface, and
the second slope is inclined such that the depth of the recessed region increases with approach toward the valley.

5 . The semiconductor device according to claim 2 , wherein the recessed region includes a pair of wall surfaces and a groove bottom located between the pair of wall surfaces in the first direction.

6 . The semiconductor device according to claim 2 , wherein the first resin surface includes a plurality of the recessed regions arranged side by side in the first direction.

7 . The semiconductor device according to claim 1 , wherein the first resin surface includes an end region on either side of the recessed region in the first direction, and
the end region is flat.

8 . The semiconductor device according to claim 7 , wherein the first terminal portion includes a first section and a second section,
the first section is located closer than the second section to the die pad portion in the first direction and covered with the sealing resin, and the second section protrudes from the second resin surface and is exposed at the end region.

9 . The semiconductor device according to claim 8 , wherein the first terminal portion includes a third section connected to the first section and the second section, and
the third section is perpendicular to each of the first section and the second section and extends in the thickness direction.

10 . The semiconductor device according to claim 8 , wherein the second terminal portion includes a fourth section and a fifth section,
the fourth section is located closer than the fifth section to the die pad portion in the first direction and covered with the sealing resin, and the fifth section protrudes from the fourth resin surface and is exposed at the end region.

11 . The semiconductor device according to claim 10 , wherein the second terminal portion includes a sixth section connected to the fourth section and the fifth section, and
the sixth section is perpendicular to each of the fourth section and the fifth section and extends in the thickness direction.

12 . The semiconductor device according to claim 10 , wherein the first terminal portion is connected at the first section to the die pad portion, and
the second terminal portion is spaced apart from the die pad portion.

13 . The semiconductor device according to claim 12 , further comprising a connecting member bonded to the semiconductor element,
wherein the connecting member is covered with the sealing resin.

14 . The semiconductor device according to claim 13 , wherein a deepest portion of the recessed region does not overlap with the connecting member as viewed in the thickness direction.

15 . The semiconductor device according to claim 14 , wherein the depth of the recessed region at the deepest portion is greater than a separation distance between the connecting member and the end region in the thickness direction.

16 . The semiconductor device according to claim 10 , wherein the depth of the recessed region at a deepest portion is greater than a thickness of each of the second section and the fifth section.

17 . The semiconductor device according to claim 1 , wherein the semiconductor element comprises a switching element or a diode.

Assignees

• Rohm Co Ltd

Inventors

• KAKIZAKI Ryotaro
• Saito Koshun

Classifications

• H10W72/851

  Dispositions of multiple connectors or interconnections · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/421

  Shapes or dispositions · CPC title