Signal isolator having enhanced creepage characteristics

Patent metadata

Field	Value
Publication number	US-2024234257-A1
Application number	US-202418618259-A
Country	US
Kind code	A1
Filing date	Mar 27, 2024
Priority date	Sep 18, 2019
Publication date	Jul 11, 2024
Grant date	—

Abstract

Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, an isolator includes a leadframe having first and second die paddles each having opposed first and second surfaces, a first die supported by the first surface of the first die paddle, and a second die supported by the first surface of the second die paddle. The first and second die paddles are configured enhanced creepage characteristics.

First claim

What is claimed is:

1 . A leadless signal isolator IC package, comprising:
a leadframe having first and second die paddles each having opposed first and second surfaces; a first die supported by the first surface of the first die paddle; and a second die supported by the first surface of the second die paddle, wherein the second surface of the first die paddle is exposed on an exterior surface of the package, and wherein the second surface of the second die paddle is exposed on the exterior surface of the package, wherein the first die has a first width and the second die has a second width, wherein a width of the second surface of the first die paddle is less than the first width of the first die along an entire length of the first die and edges of the first die along the length of the first die are outside of edges of the exposed second surface of the first die paddle, and wherein a width of the first surface of the first die paddle is greater than the first width of the die along the entire length of the first die.

2 . The signal isolator IC package according to claim 1 , wherein a width of the second surface of the second die paddle is less than the second width of the second die along an entire length of the second die and edges of the second die along the length of the second die are outside of edges of the exposed second surface of the second die paddle.

3 . The signal isolator IC package according to claim 1 , wherein the first die includes pads located within the width of the second surface of the first die paddle.

4 . The signal isolator IC package according to claim 1 , wherein the first die includes a first voltage domain and the second die includes a second voltage domain.

5 . The signal isolator package according to claim 1 , wherein the first die paddle comprises a middle portion having a first thickness and outer portions having a second thickness that is less than the first thickness.

6 . The signal isolator package according to claim 1 , wherein the first die includes pads located within the width of the second surface of the first die paddle, and further including at least one wirebond connected to at least one of the pads.

7 . A method for providing a leadless signal isolator IC package, comprising:
employing a leadframe having first and second die paddles each having opposed first and second surfaces; employing a first die supported by the first surface of the first die paddle; and employing a second die supported by the first surface of the second die paddle, wherein the second surface of the first die paddle is exposed on an exterior surface of the package, and wherein the second surface of the second die paddle is exposed on the exterior surface of the package, wherein the first die has a first width and the second die has a second width, wherein a width of the second surface of the first die paddle is less than the first width of the first die along an entire length of the first die and edges of the first die along the length of the first die are outside of edges of the exposed second surface of the first die paddle, and wherein a width of the first surface of the first die paddle is greater than the first width of the die along the entire length of the first die.

8 . The method according to claim 7 , wherein a width of the second surface of the second die paddle is less than the second width of the second die along an entire length of the second die and edges of the second die along the length of the second die are outside of edges of the exposed second surface of the second die paddle.

9 . The method according to claim 7 , wherein the first die includes pads located within the width of the second surface of the first die paddle.

10 . The method according to claim 7 , wherein the first die includes a first voltage domain and the second die includes a second voltage domain.

11 . The method according to claim 7 , wherein the first die paddle comprises a middle portion having a first thickness and outer portions having a second thickness that is less than the first thickness.

12 . The method according to claim 7 , wherein the first die includes pads located within the width of the second surface of the first die paddle, and further including at least one wirebond connected to at least one of the pads.

Assignees

• Allegro Microsystems Llc

Inventors

• Briano Robert A
• Liu Shixi Louis
• Taylor William P

Classifications

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W72/551

  Materials of bond wires · CPC title