Semiconductor memory device and electronic system including the same

Patent metadata

Field	Value
Publication number	US-2024215242-A1
Application number	US-202318475784-A
Country	US
Kind code	A1
Filing date	Sep 27, 2023
Priority date	Dec 27, 2022
Publication date	Jun 27, 2024
Grant date	—

Abstract

A semiconductor memory device may include a cell substrate, a mold structure including gate electrodes stacked on the cell substrate, a channel structures penetrating the mold structure; and a first cutting structure cutting some of the gate electrodes. The first cutting structure may include a first portion having a line shape extending in a first direction and a second portion having a line shape extending in a second direction. The first portion and the second portion may be alternately connected to form a zigzag shape. The first cutting structure may include a first side wall and a second side wall opposing the first side wall. A first point of the first side wall connected from the second portion to the first portion and a second point of the second side wall connected from the first portion to the second portion may be in corresponding channel structures among the channel structures.

First claim

1 . A semiconductor memory device comprising:
a cell substrate including a cell region and an extension region; a mold structure including a plurality of gate electrodes sequentially stacked on the cell substrate; a plurality of first channel structures penetrating the mold structure and arranged in a first direction on the cell region; a plurality of second channel structures penetrating the mold structure, the plurality of second channel structures being adjacent to the plurality of first channel structures in a second direction and arranged in the first direction on the cell region such that the plurality of first channel structures and the plurality of second channel structures are arranged in a zigzag pattern on the cell region; and a cutting structure including a first portion and a second portion that each have a line shape,
the first portion extending in a third direction from inside of each of the plurality of first channel structures to inside of each of the plurality of second channel structures adjacent to each of the plurality of first channel structures, and
the second portion extending in a fourth direction from inside of each of the plurality of second channel structures to inside of each of the plurality of first channel structures adjacent to each of the plurality of second channel structures,
the fourth direction being different from the third direction,
wherein the cutting structure cuts some of the plurality of gate electrodes.

2 . The semiconductor memory device of claim 1 , wherein
the first portion and the second portion are connected to each other, the cutting structure extends in the first direction and has a zigzag shape.

3 . The semiconductor memory device of claim 1 , wherein
the plurality of gate electrodes include a ground selection line, a plurality of word lines, and a string selection line, which are sequentially stacked on each other, and the cutting structure cuts the string selection line.

4 . The semiconductor memory device of claim 3 , wherein
the extension region and the cell region are arranged by each other in the first direction, the cutting structure extends in the first direction, and the cutting structure has a zigzag shape in at least a part of the extension region.

5 . The semiconductor memory device of claim 3 , wherein
the extension region and the cell region are arranged by each other the first direction, and the cutting structure extends in the first direction, and the cutting structure has a line shape in at least a part of the extension region.

6 . The semiconductor memory device of claim 1 , wherein
the plurality of gate electrodes include a ground selection line, a plurality of word lines and a string selection line, which are sequentially stacked on each other, and the cutting structure cuts the ground selection line.

7 . The semiconductor memory device of claim 1 ,
wherein the plurality of first channel structures, the plurality of second channel structures, and the cutting structure are arranged by each other in the second direction.

8 . The semiconductor memory device of claim 1 , further comprising:
a plurality of third channel structures penetrating the mold structure, wherein the plurality of third channel structures are spaced apart from the plurality of second channel structures in the second direction and arranged in the first direction in a zigzag arrangement.

9 . The semiconductor memory device of claim 1 , wherein
the plurality of first channel structures and the plurality of second channel structures each include a filling pattern penetrating the mold structure, a semiconductor pattern between the filling pattern and the mold structure, and an information storage film between the semiconductor pattern and the mold structure, the first portion extends from the filling pattern of each of the plurality of first channel structures to the filling pattern of the plurality of second channel structures adjacent to each of the plurality of first channel structures in the third direction, and the second portion extends from the filling pattern of each of the plurality of second channel structures to the filling pattern of each of the plurality of first channel structures adjacent to each of the plurality of second channel structures in the fourth direction.

10 . The semiconductor memory device of claim 1 , wherein
the cutting structure includes a first side wall and a second side wall opposing the first side wall, a first point of the first side wall connected from the first portion to the second portion is on a same plane as outer walls of the plurality of second channel structures or is spaced part from the plurality of second channel structures, and a second point of the second side wall connected from the second portion to the first portion is coplanar with outer walls of the plurality of first channel structures or is spaced apart from the plurality of first channel structures.

11 . A semiconductor memory device comprising:
a cell substrate; a mold structure including a plurality of gate electrodes sequentially stacked on the cell substrate; a plurality of channel structures penetrating the mold structure; and a first cutting structure cutting some of the plurality of gate electrodes, the first cutting structure including a first portion having a line shape extending in a first direction and a second portion having a line shape extending in a second direction, the first portion and the second portion being alternately connected to form a zigzag shape, wherein the first cutting structure includes a first side wall and a second side wall opposing the first side wall, and a first point of the first side wall connected from the second portion to the first portion and a second point of the second side wall connected from the first portion to the second portion are in corresponding channel structures among the plurality of channel structures.

12 . The semiconductor memory device of claim 11 , wherein
the plurality of gate electrodes include a ground selection line, a plurality of word lines, and a string selection line that are sequentially stacked along a third direction, and the first cutting structure cuts the string selection line.

13 . The semiconductor memory device of claim 12 , further comprising:
a second cutting structure cutting the ground selection line, wherein the second cutting structure includes a third portion having a line shape extending in the first direction and a fourth portion having a line shape extending in the second direction, the third portion and the fourth portion are alternately connected to form a zigzag structure, the second cutting structure includes a third side wall and a fourth side wall opposing the third side wall, and a third point of the third side wall connected from the fourth portion to the third portion, and a fourth point of the fourth side wall connected from the third portion to the fourth portion are placed inside the plurality of channel structures.

14 . The semiconductor memory device of claim 13 , wherein
the second cutting structure does not overlap the first cutting structure in the third direction.

15 . The semiconductor memory device of claim 13 , wherein
the second cutting structure overlaps at least a part of the first cutting structure in the third direction.

16 . The semiconductor memory device of claim 11 , wherein
a third point of the first side wall connected from the first portion to the second portion and a fourth point of the second side wall connected from the second portion to the fi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Gil Sung
• Sung Suk Kang

Classifications

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title