Low Temperature Fabrication of Silicon Nitride Photonic Devices

Patent metadata

Field	Value
Publication number	US-2024210625-A1
Application number	US-202318395038-A
Country	US
Kind code	A1
Filing date	Dec 22, 2023
Priority date	Dec 22, 2022
Publication date	Jun 27, 2024
Grant date	—

Abstract

Disclosed herein is methods for fabricating ultra-low loss waveguides. One particular method may include: preparing a substrate including a lower cladding layer in a deposition chamber; flowing precursors including deuterated silane and nitrogen onto the lower cladding layer in the deposition chamber; subjecting the precursors to an inductively coupled plasma-plasma enhanced chemical vapor deposition (ICP-PECVD) process which disassociates the deuterated silane and nitrogen and deposits waveguide material of silicon nitride or silicon oxynitride onto the lower cladding layer; patterning the waveguide material into a patterned waveguide material; and depositing a top cladding layer on the patterned waveguide material, wherein the ICP-PECVD process occurs at a temperature less than or equal to 250° C. Advantageously, the ICP-PECVD process allows for deposition of low hydrogenated deposition of material layers which may allow for low temperature fabrication of ultra-low loss waveguides.

First claim

What is claimed is:

1 . A method for fabricating an ultra-low loss waveguide comprising:
preparing a substrate including a lower cladding layer in a deposition chamber; flowing precursors comprising deuterated silane and nitrogen onto the lower cladding layer in the deposition chamber; subjecting the precursors to an inductively coupled plasma-plasma enhanced chemical vapor deposition (ICP-PECVD) process which disassociates the deuterated silane and nitrogen and deposits waveguide material of silicon nitride or silicon oxynitride onto the lower cladding layer; patterning the waveguide material into a patterned waveguide material; and depositing an upper cladding layer on the patterned waveguide material, wherein the ICP-PECVD process occurs at a temperature less than or equal to 250° C.

2 . The method of claim 1 , wherein the substrate comprises a substrate material selected from the group consisting of: silicon, quartz, a III-V semiconductor, and a polymer.

3 . The method of claim 1 , wherein depositing the upper cladding layer comprises flowing vapor precursors of silane, oxygen, and argon onto the lower patterned waveguide material and subjecting the vapor precursors to an ICP-PECVD process which disassociates the silane and oxygen and deposits waveguide material of silicon oxide onto the patterned waveguide material.

4 . The method of claim 1 , further comprising depositing the lower cladding layer which comprises flowing vapor precursors of deuterated silane, oxygen onto the lower patterned waveguide material and subjecting the vapor precursors to an ICP-PECVD process which disassociates the silane and oxygen and deposits waveguide material of silicon oxide onto the substrate.

5 . The method of claim 1 , wherein the waveguide material has a thickness of less than 200 nm.

6 . The method of claim 5 , wherein patterning the waveguide material comprises:
coating the waveguide material with a photoresist; exposing the photoresist through a mask to transfer a pattern onto the photoresist; etching the waveguide material through the photoresist; and removing the photoresist.

7 . The method of claim 6 , wherein etching the waveguide material is performed with a reactive ion etch process.

8 . The method of claim 7 , wherein the reactive ion etch process is an inductively coupled plasma-reactive ion etch (ICP-RIE) process, wherein the ICP-RIE process is performed at a temperature of 250° C. or less.

9 . The method of claim 1 , wherein the waveguide material has a thickness of greater than or equal to 200 nm.

10 . The method of claim 9 , wherein patterning the waveguide material comprises:
depositing a hard mask layer on the waveguide material; coating the hard mask layer with a photoresist; exposing the photoresist through a mask to transfer a pattern onto the photoresist; etching the hard mask layer through the photoresist; removing the photoresist; etching the waveguide material through the hard mask layer; and removing the hard mask layer.

11 . The method of claim 10 , wherein etching the waveguide material is performed with a reactive ion etch process.

12 . The method of claim 11 , wherein the reactive ion etch process is an inductively coupled plasma-reactive ion etch (ICP-RIE) process, wherein the ICP-RIE process is performed at a temperature of 250° C. or less.

13 . The method of claim 10 , wherein depositing the hard mask layer comprises sputtering a hard mask material onto the waveguide material.

14 . The method of claim 10 , wherein etching the hard mask layer is performed with a reactive ion etch process.

15 . The method of claim 14 , wherein the reactive ion etch process is an inductively coupled plasma-reactive ion etch (ICP-RIE) process, wherein the ICP-RIE process is performed at a temperature of 250° C. or less.

16 . The method of claim 1 , further comprising:
flowing precursors comprising deuterated silane and nitrogen onto the upper cladding layer in the deposition chamber; subjecting the precursors to an ICP-PECVD process which disassociates the deuterated silane and nitrogen and deposits waveguide material of silicon nitride or silicon oxynitride onto the upper cladding layer; and patterning the waveguide material into a second patterned waveguide material.

17 . A heterogeneously integrated ultra-low loss optical waveguide comprising:
a substrate comprising electronic or photonic circuits in a material system that is not compatible with high temperature processing above 250° C.; a lower cladding layer positioned on top of the lower substrate fabricated with a maximum temperature of 250° C.; a first waveguide core layer positioned on top of the lower cladding layer fabricated with a maximum temperature of 250° C.; and a first upper cladding layer positioned on top of the waveguide core layer fabricated with a maximum temperature of 250° C.

18 . The optical waveguide of claim 17 , wherein the substrate is selected from the group consisting of: silicon photonics, electronic circuits, printed circuit boards, organic circuits, lithium niobate, barium titanium oxide (BTO), quartz, sapphire, and silicon carbide.

19 . The optical waveguide of claim 17 , wherein the first waveguide core layer is a nitride layer including a thickness from 20 nm to 1 micron with maximum processing temperature of 250° C.

20 . The optical waveguide of claim 17 , further comprising a second waveguide core layer positioned on the first upper cladding layer and a second upper cladding layer positioned on the second waveguide core, wherein the second waveguide core and the second upper cladding layer are fabricated with a maximum processing temperature of 250° C.

Assignees

• Univ California

Inventors

• Bose Debapam
• Wang Jiawei
• Blumenthal Daniel J

Classifications

• C23C16/505

  using radio frequency discharges · CPC title

• C23C16/308

  Oxynitrides · CPC title

• C23C16/345

  Silicon nitride · CPC title

• G02B6/136 Primary

  by etching · CPC title

• G02B6/132 Primary

  by deposition of thin films · CPC title